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1. 发明授权

US08319289B2 Power MISFET, semiconductor device and DC/DC converter 有权
标题翻译：电源MISFET，半导体器件和DC / DC转换器
公开(公告)号：US08319289B2
公开(公告)日：2012-11-27
申请号：US12005918
申请日：2007-12-27
申请人： Masaki Shiraishi , Noboru Akiyama , Takayuki Hashimoto
发明人： Masaki Shiraishi , Noboru Akiyama , Takayuki Hashimoto
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7816 , H01L21/823814 , H01L21/823878 , H01L27/0922 , H01L29/0653 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/402 , H01L29/456 , H01L29/665 , H01L29/66689
摘要： A technique for suppressing lowering of withstand voltage and lowering of breakdown resistance and reducing a feedback capacitance of a power MISFET is provided. A lateral power MISFET that comprises a trench region whose insulating layer is formed shallower than an HV-Nwell layer is provided in the HV-Nwell layer (drift region) formed on a main surface of a semiconductor substrate in a direction from the main surface to the inside. The lateral power MISFET has an arrangement on a plane of the main surface including a source layer (source region) and a drain layer (drain region) arranged at opposite sides to each other across a gate electrode (first conducting layer), and a dummy gate electrode (second conducting layer) that is different from the gate electrode is arranged between the gate electrode and the drain layer.
摘要翻译：提供了用于抑制耐压降低和击穿电阻降低并降低功率MISFET的反馈电容的技术。在半导体衬底的主表面上形成的HV-Nwell层（漂移区域）中，沿着从主表面到主体表面的方向，设置包括其绝缘层形成为比HV-Nwell层浅的沟槽区域的横向功率MISFET 里面。横向功率MISFET具有在主表面的平面上的布置，包括在栅极电极（第一导电层）上彼此相对设置的源极层（源极区域）和漏极层（漏极区域）与栅电极不同的栅电极（第二导电层）配置在栅电极和漏极层之间。

2. 发明授权

US08258711B2 Semiconductor device, LED driving circuit, and apparatus for displaying an image 失效
标题翻译：半导体装置，LED驱动电路以及显示图像的装置
公开(公告)号：US08258711B2
公开(公告)日：2012-09-04
申请号：US12779343
申请日：2010-05-13
申请人： Noboru Akiyama , Takayuki Hashimoto , Takashi Hirao , Nobuyoshi Matsuura , Hideo Ishii
发明人： Noboru Akiyama , Takayuki Hashimoto , Takashi Hirao , Nobuyoshi Matsuura , Hideo Ishii
IPC分类号： H05B37/02
CPC分类号： H01L29/7813 , G09G3/342 , G09G2320/064 , H01L29/0615 , H01L29/0619 , H01L29/41766 , H01L29/7803 , H01L29/7811 , H01L29/7815 , H05B33/0818 , H05B33/0827 , H05B33/089 , Y02B20/347
摘要： The semiconductor device is included in the LED driving circuit (current regulator) of driving the LED array (with series-connected number m×parallel-connected number n), and is formed of a plurality (n pieces) of LED driving devices of controlling a current (constant-current driving) flowing in each string. A vertical semiconductor device, for example, a vertical MOSFET is used as the LED driving device. Both of a main device functioning as a constant-current driving device and a subsidiary device functioning as a circuit-breaking switch during dimming are formed inside a chip of the device, which are formed of the vertical semiconductor devices. In a first surface of the device, each source region of the main device and the subsidiary device is formed so as to be insulated from each other through an isolation region.
摘要翻译：半导体器件包括在驱动LED阵列（串联数字×并联数n）的LED驱动电路（电流调节器）中，并且由多个（n个）LED驱动装置形成，在每个串中流动的电流（恒流驱动）。使用垂直半导体器件，例如垂直MOSFET作为LED驱动器件。作为恒流驱动装置的主装置和在调光期间用作断路开关的辅助装置都形成在由垂直半导体装置形成的装置的芯片的内部。在装置的第一表面中，主装置和附属装置的每个源区形成为通过隔离区彼此绝缘。

3. 发明授权

US08203380B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US08203380B2
公开(公告)日：2012-06-19
申请号：US12483668
申请日：2009-06-12
申请人： Takayuki Hashimoto , Takashi Hirao , Noboru Akiyama
发明人： Takayuki Hashimoto , Takashi Hirao , Noboru Akiyama
IPC分类号： H01L25/00
CPC分类号： H01L27/0629 , H01L2924/0002 , H02M7/003 , H01L2924/00
摘要： In a semiconductor device, a high-side driver is arranged in a region closer to a periphery of a semiconductor substrate than a high-side switch, and a low-side driver is arranged in a region closer to the periphery of the semiconductor substrate than the low-side switch. By this means, a path from a positive terminal of an input capacitor to a negative terminal of the input capacitor via the high-side switch and the low-side switch is short, a path from a positive terminal of a drive capacitor to a negative terminal of the drive capacitor via the low-side driver is short, and a path from a positive terminal of a boot strap capacitor to a negative terminal of the boot strap capacitor via the high-side driver is short, and therefore, the parasitic inductance can be reduced, and the conversion efficiency can be improved.
摘要翻译：在半导体装置中，高侧驱动器配置在比高侧开关更靠近半导体基板的周围的区域，低边驱动器配置在比半导体基板的周边更靠近的区域，低端开关。通过这种方式，经由高侧开关和低侧开关从输入电容器的正极端子到输入电容器的负极端子的路径很短，从驱动电容器的正极端子到负极的路径通过低侧驱动器的驱动电容器的端子短，通过高侧驱动器从引导电容器的正极端子到引导电容器的负极端子的路径短，因此，寄生电感可以降低转换效率。

4. 发明申请

US20120001609A1 DC/DC CONVERTER 有权
标题翻译： DC / DC转换器
公开(公告)号：US20120001609A1
公开(公告)日：2012-01-05
申请号：US13230947
申请日：2011-09-13
申请人： Masaki SHIRAISHI , Takayuki Hashimoto , Noboru Akiyama
发明人： Masaki SHIRAISHI , Takayuki Hashimoto , Noboru Akiyama
IPC分类号： G05F1/46
CPC分类号： H02M1/08 , H01L24/48 , H01L24/49 , H01L2224/48137 , H01L2224/48247 , H01L2224/49175 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01033 , H01L2924/01082 , H01L2924/12032 , H01L2924/12036 , H01L2924/13091 , H01L2924/14 , H01L2924/30107 , H03K17/0822 , H03K17/165 , H03K17/166 , H03K17/6871 , H01L2924/00 , H01L2224/45099
摘要： In a non-isolated DC/DC converter, a reference potential for a low-side pre-driver which drives a gate of a low-side MOSFET is applied from a portion except for a main circuit passing through a high-side MOSFET and the low-side MOSFET so that a parasitic inductance between a source of the low-side MOSFET and the pre-driver is increased without increasing the sum of parasitic inductances in the main circuit and negative potential driving of the gate of the low-side MOSFET can be performed and a self turn-on phenomenon can be prevented without adding any member and changing drive system.
摘要翻译：在非隔离型DC / DC转换器中，从通过高侧MOSFET的主电路以外的部分施加驱动低侧MOSFET的栅极的低侧预驱动器的基准电位，低侧MOSFET，使得低侧MOSFET的源极与预驱动器之间的寄生电感增加，而不增加主电路中的寄生电感的和，并且低侧MOSFET的栅极的负电位驱动并且可以防止在不添加任何构件和改变驱动系统的情况下自启闭现象。

5. 发明申请

US20110278655A1 Semiconductor Device with Circuit for Reduced Parasitic Inductance 审中-公开
标题翻译：具有降低寄生电感的电路的半导体器件
公开(公告)号：US20110278655A1
公开(公告)日：2011-11-17
申请号：US13192584
申请日：2011-07-28
申请人： Takayuki Hashimoto , Noboru Akiyama , Masaki Shiraishi , Tetsuya Kawashima
发明人： Takayuki Hashimoto , Noboru Akiyama , Masaki Shiraishi , Tetsuya Kawashima
IPC分类号： H01L27/06
CPC分类号： H01L25/16 , G06F1/26 , H01L24/48 , H01L24/49 , H01L2224/0603 , H01L2224/40 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49175 , H01L2924/00014 , H01L2924/01023 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： Parasitic inductance of the main circuit of a power source unit is reduced. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are electrically connected via the same die pad.
摘要翻译：降低了电源单元主电路的寄生电感。在具有用于高侧开关的功率MOSFET和低侧开关的功率MOSFET串联的电路的非绝缘DC-DC转换器中，用于高侧开关的功率MOSFET和用于低侧开关的功率MOSFET是由n沟道垂直MOSFET形成，并且用于高侧开关的功率MOSFET的源极和用于低侧开关的功率MOSFET的漏电极经由相同的管芯焊盘电连接。

6. 发明申请

US20100327348A1 SEMICONDUCTOR DEVICE, METHOD OF MANUFACTURING THE SAME AND POWER-SUPPLY DEVICE USING THE SAME 失效
标题翻译：半导体器件及其制造方法和使用该电极的电源装置
公开(公告)号：US20100327348A1
公开(公告)日：2010-12-30
申请号：US12818485
申请日：2010-06-18
申请人： Takayuki HASHIMOTO , Takashi HIRAO , Noboru AKIYAMA
发明人： Takayuki HASHIMOTO , Takashi HIRAO , Noboru AKIYAMA
IPC分类号： H01L27/06 , H01L21/8234 , H01L29/78
CPC分类号： H01L29/7802 , H01L21/26586 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/405 , H01L29/407 , H01L29/41741 , H01L29/41766 , H01L29/41775 , H01L29/4933 , H01L29/66727 , H01L29/7803 , H02M3/1588 , Y02B70/1466
摘要： In a lateral-type power MOSFET, high breakdown voltage is achieved with suppressing to increase a cell pitch, and a feedback capacity and an ON resistance are decreased. An n− type silicon region having a high resistance to be a region of maintaining a breakdown voltage is vertically provided with respect to a main surface of an n+ type silicon substrate, and the n− type silicon region having the high resistance is connected to the n+ type silicon substrate. Also, a conductive substance is filled through an insulating substance inside a trench formed to reach the n+ type silicon substrate from the main surface of the n+ type silicon substrate so as to contact with the n− type silicon region having the high resistance, and the conductive substance is electrically connected to a source electrode.
摘要翻译：在横向型功率MOSFET中，通过抑制增加电池间距而实现高的击穿电压，并且降低反馈容量和导通电阻。相对于n +型硅衬底的主表面垂直地设置具有高电阻的n型硅区域作为保持击穿电压的区域，并且具有高电阻的n型硅区域连接到 n +型硅衬底。此外，导电物质通过绝缘物质填充在形成为从n +型硅衬底的主表面到达n +型硅衬底的沟槽内，以便与具有高电阻的n型硅区接触，并且导电物质电连接到源电极。

7. 发明申请

US20100176430A1 Semiconductor Device with Reduced Parasitic Inductance 有权
标题翻译：具有降低寄生电感的半导体器件
公开(公告)号：US20100176430A1
公开(公告)日：2010-07-15
申请号：US12721201
申请日：2010-03-10
申请人： Takayuki Hashimoto , Noboru Akiyama , Masaki Shiraishi , Tetsuya Kawashima
发明人： Takayuki Hashimoto , Noboru Akiyama , Masaki Shiraishi , Tetsuya Kawashima
IPC分类号： H01L27/06
CPC分类号： H01L25/16 , G06F1/26 , H01L24/48 , H01L24/49 , H01L2224/0603 , H01L2224/40 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/49111 , H01L2224/49175 , H01L2924/00014 , H01L2924/01023 , H01L2924/01033 , H01L2924/01074 , H01L2924/01082 , H01L2924/12032 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/181 , H01L2924/19105 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/05599
摘要： The present invention provides a technology for reducing the parasitic inductance of the main circuit of a power source unit. In a non-insulated DC-DC converter having a circuit in which a power MOSFET for high side switch and a power MOSFET for low side switch are connected in series, the power MOSFET for high side switch and the power MOSFET for low side switch are formed of n-channel vertical MOSFETs, and a source electrode of the power MOSFET for high side switch and a drain electrode of the power MOSFET for low side switch are
摘要翻译：本发明提供一种降低电源单元的主电路的寄生电感的技术。在具有用于高侧开关的功率MOSFET和低侧开关的功率MOSFET串联的电路的非绝缘DC-DC转换器中，用于高侧开关的功率MOSFET和用于低侧开关的功率MOSFET是由n沟道垂直MOSFET形成，用于高侧开关的功率MOSFET的源极和用于低边开关的功率MOSFET的漏电极

8. 发明申请

US20080315851A1 SEMICONDUCTOR DEVICE AND POWER SUPPLY USING THE SAME 有权
标题翻译：半导体器件和使用该器件的电源
公开(公告)号：US20080315851A1
公开(公告)日：2008-12-25
申请号：US12143305
申请日：2008-06-20
申请人： Noboru Akiyama , Takayuki Hashimoto , Takashi Hirao , Koji Tateno
发明人： Noboru Akiyama , Takayuki Hashimoto , Takashi Hirao , Koji Tateno
IPC分类号： G05F1/10
CPC分类号： H02M3/1588 , Y02B70/1466
摘要： A power-supply control IC is included in a switching power supply which drives to turn on and off a semiconductor switching device connected to a DC power supply in series to supply a predetermined constant voltage to an external load, and is a semiconductor device including a semiconductor circuit which controls on and off of the semiconductor switching device. When a current flowing through the load is abruptly increased to cause an error voltage to exceed a predetermined first threshold voltage after the end of a PWM on-pulse generated in synchronization with a switching cycle, a second PWM on-pulse is generated within the same switching cycle. Furthermore, in a plurality of switching cycles after the switching cycle in which the second PWM on-pulse is generated, the first threshold voltage for comparison with the error voltage is switched to a second threshold voltage higher than the first threshold voltage.
摘要翻译：电源控制IC包括在开关电源中，该开关电源驱动以串联连接到直流电源的半导体开关装置，以向外部负载提供预定的恒定电压，并且是包括控制半导体开关器件的导通和截止的半导体电路。当流过负载的电流突然增加以在与开关周期同步产生的PWM导通脉冲结束之后导致误差电压超过预定的第一阈值电压时，在同一时间内产生第二PWM导通脉冲开关周期。此外，在产生第二PWM导通脉冲的开关周期之后的多个开关周期中，与误差电压进行比较的第一阈值电压被切换到高于第一阈值电压的第二阈值电压。

9. 发明申请

US20080023758A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080023758A1
公开(公告)日：2008-01-31
申请号：US11863556
申请日：2007-09-28
申请人： Masaki Shiraishi , Noboru Akiyama , Tomoaki Uno , Nobuyoshi Matsuura
发明人： Masaki Shiraishi , Noboru Akiyama , Tomoaki Uno , Nobuyoshi Matsuura
IPC分类号： H01L29/78
CPC分类号： G05F3/08 , H01L23/3107 , H01L23/4824 , H01L23/49551 , H01L23/49562 , H01L23/49575 , H01L24/06 , H01L24/37 , H01L24/40 , H01L24/41 , H01L24/45 , H01L24/48 , H01L24/49 , H01L25/072 , H01L25/16 , H01L29/1095 , H01L29/4175 , H01L29/41758 , H01L29/41766 , H01L29/4238 , H01L29/7811 , H01L29/7813 , H01L29/7835 , H01L2224/05554 , H01L2224/05644 , H01L2224/05647 , H01L2224/0603 , H01L2224/371 , H01L2224/37124 , H01L2224/37147 , H01L2224/40095 , H01L2224/40245 , H01L2224/40247 , H01L2224/45144 , H01L2224/48091 , H01L2224/48095 , H01L2224/48137 , H01L2224/48247 , H01L2224/48644 , H01L2224/48647 , H01L2224/49111 , H01L2224/49171 , H01L2224/49175 , H01L2224/49431 , H01L2224/73221 , H01L2224/84801 , H01L2224/8485 , H01L2224/85375 , H01L2924/01002 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/0102 , H01L2924/01022 , H01L2924/01023 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/0103 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01051 , H01L2924/01056 , H01L2924/01059 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/01083 , H01L2924/014 , H01L2924/07802 , H01L2924/12032 , H01L2924/12036 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/19041 , H01L2924/19105 , H01L2924/30105 , H01L2924/30107 , H01L2924/3011 , H02M7/003 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： The object of the present invention is to reduce parasitic inductance of a main circuit in a power supply circuit. The present invention provides a non-insulated DC-DC converter having a circuit in which a power MOS•FET for a high-side switch and a power MOS•FET for a low-side switch are connected in series. In the non-insulated DC-DC converter, the power MOS•FET for the high-side switch is formed by a p channel vertical MOS•FET, and the power MOS•FET for the low-side switch is formed by an n channel vertical MOS•FET. Thus, a semiconductor chip formed with the power MOS•FET for the high-side switch and a semiconductor chip formed with the power MOS•FET for the low-side switch are mounted over the same die pad and electrically connected to each other through the die pad.
摘要翻译：本发明的目的是减少电源电路中的主电路的寄生电感。本发明提供一种非绝缘DC-DC转换器，其具有用于高侧开关的功率MOSFET和用于低侧开关的功率MOS.FET串联连接的电路。在非绝缘DC-DC转换器中，用于高侧开关的功率MOS.FET由p沟道垂直MOSFET形成，低边开关的功率MOS.FET由n沟道垂直 MOS.FET。因此，形成有用于高侧开关的功率MOS.FET和形成有用于低侧开关的功率MOSFET的半导体芯片的半导体芯片安装在相同的芯片焊盘上，并通过芯片垫

10. 发明申请

US20070200537A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20070200537A1
公开(公告)日：2007-08-30
申请号：US11624767
申请日：2007-01-19
申请人： Noboru Akiyama , Takayuki Hashimoto , Masaki Shiraishi , Tetsuya Kawashima , Koji Tateno , Nobuyoshi Matsuura
发明人： Noboru Akiyama , Takayuki Hashimoto , Masaki Shiraishi , Tetsuya Kawashima , Koji Tateno , Nobuyoshi Matsuura
IPC分类号： G05F1/10 , H02J3/12
CPC分类号： H01L25/16 , H01L24/37 , H01L24/40 , H01L2224/05554 , H01L2224/37124 , H01L2224/37147 , H01L2224/40245 , H01L2224/40247 , H01L2224/45144 , H01L2224/48091 , H01L2224/48137 , H01L2224/48247 , H01L2224/48472 , H01L2224/49171 , H01L2224/49175 , H01L2224/73221 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/1306 , H01L2924/13091 , H01L2924/181 , H01L2924/19105 , H01L2924/30107 , H02M3/1588 , H03K17/08142 , H03K17/162 , H03K17/6871 , H03K2217/0036 , Y02B70/1466 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A power supply capable of reducing loss of large current and high frequency. In an MCM for power supply in which a high-side power MOSFET chip, a low-side power MOSFET chip and a driver IC chip driving them are sealed in one sealing material (a capsulating insulation resin), a wiring length of a wiring DL connecting an output terminal of the driver IC chip to a gate terminal of the low-side power MOSFET chip or a source terminal is made shorter than a wiring length of a wiring DH connecting the output terminal of the driver IC chip to a gate terminal of the high-side power MOSFET chip or a source terminal. Further, the number of the wiring DL is made larger than the number of the wiring DH.
摘要翻译：一种能够减少大电流和高频损耗的电源。在用于电源的MCM中，高边功率MOSFET芯片，低边功率MOSFET芯片和驱动IC芯片驱动它们被密封在一个密封材料（封装绝缘树脂）中，布线DL的布线长度将驱动IC芯片的输出端子与低边功率MOSFET芯片的栅极端子或源极端子连接的距离比连接驱动器IC芯片的输出端子的栅极端子的布线长度短高端功率MOSFET芯片或源极端子。此外，使布线数量DL大于布线数量DH。

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