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1. 发明申请

US20130313623A1 THRESHOLD GATE AND THRESHOLD LOGIC ARRAY 有权
标题翻译：阈值门和阈值逻辑阵列
公开(公告)号：US20130313623A1
公开(公告)日：2013-11-28
申请号：US13903490
申请日：2013-05-28
申请人： Sarma Vrudhula , Nishant S. Nukala , Niranjan Kulkarni
发明人： Sarma Vrudhula , Nishant S. Nukala , Niranjan Kulkarni
IPC分类号： H01L43/02
CPC分类号： H01L43/02 , H03K19/18 , H03K19/20 , H03K19/23
摘要： Threshold gates and related circuitry are disclosed. In one embodiment, a threshold gate includes a threshold realization element and a magnetic tunnel junction (MTJ) element. The MTJ element is switchable from a first resistive state to a second resistive state. To realize a threshold function with the MTJ element, the threshold realization element is configured to switch the magnetic tunnel junction element from the first resistive state to the second resistive state in accordance with the threshold function. In this manner, the threshold gate may implement a threshold function that provides an output just like a complex Boolean function requiring several Boolean gates.
摘要翻译：公开了阈值门和相关电路。在一个实施例中，阈值门包括阈值实现元件和磁性隧道结（MTJ）元件。 MTJ元件可从第一电阻状态切换到第二电阻状态。为了实现具有MTJ元件的阈值函数，阈值实现元件被配置为根据阈值函数将磁隧道结元件从第一电阻状态切换到第二电阻状态。以这种方式，阈值门可以实现提供输出的阈值函数，就像需要几个布尔门的复数布尔函数。

2. 发明授权

US09876503B2 Method of obfuscating digital logic circuits using threshold voltage 有权
公开(公告)号：US09876503B2
公开(公告)日：2018-01-23
申请号：US15390970
申请日：2016-12-27
申请人： Sarma Vrudhula , Aykut Dengi , Niranjan Kulkarni , Joseph Davis
发明人： Sarma Vrudhula , Aykut Dengi , Niranjan Kulkarni , Joseph Davis
IPC分类号： H03K19/20 , H03K19/08 , H03K19/096 , H03K19/21
CPC分类号： H03K19/0813 , H03K19/0963 , H03K19/21
摘要： A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.

3. 发明授权

US10250236B2 Energy efficient, robust differential mode d-flip-flop 有权
公开(公告)号：US10250236B2
公开(公告)日：2019-04-02
申请号：US15575611
申请日：2016-05-23
申请人： Sarma Vrudhula , Niranjan Kulkarni , Jinghua Yang
发明人： Sarma Vrudhula , Niranjan Kulkarni , Jinghua Yang
IPC分类号： H03K3/037 , H03K3/012 , H03K3/356
摘要： A differential sense flip flop (DSFF) that is named the Kulkarni Vrudhula flip flop (KVFF) is disclosed. In one embodiment, the DSFF includes a differential sense amplifier and an SR latch. The differential sense amplifier includes a first amplifier branch having a first output node, a second amplifier branch having a second, a first switchable discharge path, and a second switchable discharge path. The first switchable discharge path is closed to discharge the first output node when first output node is being discharged by the first amplifier branch and the second switchable discharge path is closed to discharge the second output node when second output node is being discharged by the second amplifier branch. This prevents the output nodes from floating and increases the reliability and robustness of the DSFF.

4. 发明申请

US20170248989A1 CLOCK SKEWING STRATEGY TO REDUCE DYNAMIC POWER AND ELIMINATE HOLD-TIME VIOLATIONS IN SYNCHRONOUS DIGITAL VLSI DESIGNS 审中-公开
公开(公告)号：US20170248989A1
公开(公告)日：2017-08-31
申请号：US15443444
申请日：2017-02-27
申请人： Sarma Vrudhula , Aykut Dengi , Niranjan Kulkarni
发明人： Sarma Vrudhula , Aykut Dengi , Niranjan Kulkarni
IPC分类号： G06F1/12 , G06F1/10
CPC分类号： G06F1/12 , G06F1/10
摘要： This disclosure relates generally to digital synchronous circuits that introduce clock skew without requiring clock buffers in a clock network. In one embodiment, the digital synchronous circuit includes a first flip flop and a second flip flop. The first flip flop is synchronized to be transparent and to be opaque in accordance with a first clock signal while the second flip flop is configured such that the second flip flop is synchronized to be transparent and to be opaque in accordance with a second clock signal. However, the second flip flop is configured to generate the first clock signal such that the second flip flop provides the first clock signal in a first clock state in response the second flip flop becoming transparent and provides the first clock signal in a second clock state in response the second flip flop becoming opaque thereby providing a clock skew without clock buffers.

5. 发明申请

US20170187382A1 METHOD OF OBFUSCATING DIGITAL LOGIC CIRCUITS USING THRESHOLD VOLTAGE 有权
公开(公告)号：US20170187382A1
公开(公告)日：2017-06-29
申请号：US15390970
申请日：2016-12-27
申请人： Sarma Vrudhula , Aykut Dengi , Niranjan Kulkarni , Joseph Davis
发明人： Sarma Vrudhula , Aykut Dengi , Niranjan Kulkarni , Joseph Davis
IPC分类号： H03K19/08 , H03K19/21 , H03K19/096
CPC分类号： H03K19/0813 , H03K19/0963 , H03K19/21
摘要： A threshold logic element (TLE) is disclosed. The TLE includes a first input gate network, a second input gate network, and a differential sense amplifier. The first input gate network is configured to receive a first set of logical signals and the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. To obfuscate the TLE, any number of obfuscated transmission gates can be provided in one or both of the input gate networks. The obfuscated transmission gates are obfuscated such that obfuscated transmission gates are incapable of effecting the threshold logic function of the TLE and thus hide the functionality of the TLE.

6. 发明授权

US09356598B2 Threshold logic gates with resistive networks 有权
标题翻译：具有电阻网络的门限逻辑门
公开(公告)号：US09356598B2
公开(公告)日：2016-05-31
申请号：US14792163
申请日：2015-07-06
申请人： Sarma Vrudhula , Jinghua Yang , Niranjan Kulkarni , Shimeng Yu
发明人： Sarma Vrudhula , Jinghua Yang , Niranjan Kulkarni , Shimeng Yu
IPC分类号： G11C7/06 , H03K19/23 , H03K19/00 , G11C13/00 , G06F17/50 , H03K19/08 , H03K19/017 , H03K19/21 , G11C17/16 , G11C17/18
CPC分类号： H03K19/0013 , G06F17/505 , G06F17/5068 , G06F2217/12 , G11C7/065 , G11C13/0002 , G11C13/003 , G11C13/004 , G11C17/165 , G11C17/18 , G11C2013/0042 , G11C2213/71 , G11C2213/79 , H03K19/0027 , H03K19/01707 , H03K19/0813 , H03K19/215 , Y02P90/265
摘要： This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.
摘要翻译：本公开一般涉及用于集成电路（IC）的阈值逻辑元件。在一个实施例中，阈值逻辑元件具有第一输入门网络，第二输入门网络，差分读出放大器和电阻网络。第一输入门网络被配置为接收第一组逻辑信号，而第二输入门网络被配置为接收第二组逻辑信号。差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联，使得差分读出放大器被配置为根据阈值逻辑功能产生差分输出。电阻网络耦合在差分读出放大器和第一输入门网络之间以及差分读出放大器与第二输入门网络之间。电阻网络使门限逻辑元件不易受工艺变化的影响。

7. 发明申请

US20160006438A1 THRESHOLD LOGIC ELEMENT WITH STABILIZING FEEDBACK 有权
标题翻译：具有稳定反馈的阈值逻辑单元
公开(公告)号：US20160006438A1
公开(公告)日：2016-01-07
申请号：US14792183
申请日：2015-07-06
申请人： Sarma Vrudhula , Niranjan Kulkarni
发明人： Sarma Vrudhula , Niranjan Kulkarni
IPC分类号： H03K19/003 , H03K19/00
CPC分类号： H03K19/00361 , G11C7/065 , G11C11/1673 , G11C13/004 , H03K19/0027 , H03K19/01707 , H03K19/0963 , H03K19/215
摘要： Threshold logic elements and methods of operating the same are disclosed. In one embodiment, a threshold logic element includes a first input gate network configured to receive a first set of logical signals, a second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential logical output in accordance with a threshold logic function. In order to make the threshold logic element more robust, the differential sense amplifier is configured to feed back the differential logical output to the first input gate network and the second input gate network. By providing the differential logical output as feedback, floating node issues are avoided and the threshold logic element is more resistant to noise.
摘要翻译：公开了阈值逻辑元件及其操作方法。在一个实施例中，阈值逻辑元件包括被配置为接收第一组逻辑信号的第一输入门网络，配置成接收第二组逻辑信号的第二输入门网络。差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联，使得差分读出放大器被配置为根据阈值逻辑功能产生差分逻辑输出。为了使阈值逻辑元件更稳健，差分读出放大器被配置为将差分逻辑输出反馈到第一输入门网络和第二输入门网络。通过提供差分逻辑输出作为反馈，避免了浮动节点问题，并且阈值逻辑元件更能抵抗噪声。

8. 发明申请

US20160006437A1 THRESHOLD LOGIC GATES WITH RESISTIVE NETWORKS 有权
标题翻译：带有电阻网络的门限逻辑门
公开(公告)号：US20160006437A1
公开(公告)日：2016-01-07
申请号：US14792163
申请日：2015-07-06
申请人： Sarma Vrudhula , Jinghua Yang , Niranjan Kulkarni , Shimeng Yu
发明人： Sarma Vrudhula , Jinghua Yang , Niranjan Kulkarni , Shimeng Yu
IPC分类号： H03K19/00 , G11C13/00
CPC分类号： H03K19/0013 , G06F17/505 , G06F17/5068 , G06F2217/12 , G11C7/065 , G11C13/0002 , G11C13/003 , G11C13/004 , G11C17/165 , G11C17/18 , G11C2013/0042 , G11C2213/71 , G11C2213/79 , H03K19/0027 , H03K19/01707 , H03K19/0813 , H03K19/215 , Y02P90/265
摘要： This disclosure relates generally to threshold logic elements for integrated circuits (ICs). In one embodiment, a threshold logic element has a first input gate network, a second input gate network, a differential sense amplifier, and a resistive network. The first input gate network is configured to receive a first set of logical signals, while the second input gate network configured to receive a second set of logical signals. The differential sense amplifier is operably associated with the first input gate network and the second input gate network such that the differential sense amplifier is configured to generate a differential output in accordance with a threshold logic function. The resistive network is coupled between the differential sense amplifier and the first input gate network and between the differential sense amplifier and the second input gate network. The resistive network makes the threshold logic element less susceptible to process variations.
摘要翻译：本公开一般涉及用于集成电路（IC）的阈值逻辑元件。在一个实施例中，阈值逻辑元件具有第一输入门网络，第二输入门网络，差分读出放大器和电阻网络。第一输入门网络被配置为接收第一组逻辑信号，而第二输入门网络被配置为接收第二组逻辑信号。差分读出放大器可操作地与第一输入门网络和第二输入门网络相关联，使得差分读出放大器被配置为根据阈值逻辑功能产生差分输出。电阻网络耦合在差分读出放大器和第一输入门网络之间以及差分读出放大器与第二输入门网络之间。电阻网络使门限逻辑元件不易受工艺变化的影响。

9. 发明授权

US08832614B2 Technology mapping for threshold and logic gate hybrid circuits 有权
标题翻译：门限逻辑门混合电路的技术映射
公开(公告)号：US08832614B2
公开(公告)日：2014-09-09
申请号：US13903424
申请日：2013-05-28
申请人： Sarma Vrudhula , Niranjan Kulkarni
发明人： Sarma Vrudhula , Niranjan Kulkarni
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/505 , G06F17/10 , G06F17/5022 , G06F17/5068
摘要： A method of mapping threshold gate cells into a Boolean network is disclosed. In one embodiment, cuts are enumerated within the Boolean network. Next, a subset of the cuts within the Boolean network that are threshold is identified. To minimize power, cuts in the subset of the cuts are selected.
摘要翻译：公开了将门限门限映射到布尔网络中的方法。在一个实施例中，在布尔网络内枚举切割。接下来，识别布尔网络内的阈值子集。为了最小化功率，选择切割子集中的切割。

10. 发明申请

US20130339914A1 TECHNOLOGY MAPPING FOR THRESHOLD AND LOGIC GATE HYBRID CIRCUITS 有权
标题翻译：用于阈值和逻辑门混合电路的技术映射
公开(公告)号：US20130339914A1
公开(公告)日：2013-12-19
申请号：US13903424
申请日：2013-05-28
申请人： Sarma Vrudhula , Niranjan Kulkarni
发明人： Sarma Vrudhula , Niranjan Kulkarni
IPC分类号： G06F17/50
CPC分类号： G06F17/505 , G06F17/10 , G06F17/5022 , G06F17/5068
摘要： A method of mapping threshold gate cells into a Boolean network is disclosed. In one embodiment, cuts are enumerated within the Boolean network. Next, a subset of the cuts within the Boolean network that are threshold is identified. To minimize power, cuts in the subset of the cuts are selected.
摘要翻译：公开了将门限门限映射到布尔网络中的方法。在一个实施例中，在布尔网络内枚举切割。接下来，识别布尔网络内的阈值子集。为了最小化功率，选择切割子集中的切割。

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