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1. 发明授权

US07545900B2 Low jitter and/or fast lock-in clock recovery circuit 失效
标题翻译：低抖动和/或快速锁定时钟恢复电路
公开(公告)号：US07545900B2
公开(公告)日：2009-06-09
申请号：US11273940
申请日：2005-11-15
申请人： Ho-Ming Leung , Nasima Parveen , Ka-Shu Ko
发明人： Ho-Ming Leung , Nasima Parveen , Ka-Shu Ko
IPC分类号： H03D3/24
CPC分类号： H03L7/113 , H03L7/107 , H03L7/1075 , H04L7/033
摘要： An apparatus comprising an oscillator circuit, a control circuit, a counter circuit and a detector circuit. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to a control signal. The control circuit may be configured to generate the control signal in response to a first error signal and a second error signal. The counter circuit may be configured to generate the first error signal in response to the output signal and an input signal. The detector circuit may be configured to generate the second error signal in response to the output signal and the input signal.
摘要翻译：一种包括振荡器电路，控制电路，计数器电路和检测器电路的装置。振荡器电路可以被配置为响应于控制信号而产生以特定频率振荡的输出信号。控制电路可以被配置为响应于第一误差信号和第二误差信号而产生控制信号。计数器电路可以被配置为响应于输出信号和输入信号产生第一误差信号。检测器电路可以被配置为响应于输出信号和输入信号而产生第二误差信号。

2. 发明申请

US20070110206A1 Low jitter and/or fast lock-in clock recovery circuit 失效
标题翻译：低抖动和/或快速锁定时钟恢复电路
公开(公告)号：US20070110206A1
公开(公告)日：2007-05-17
申请号：US11273940
申请日：2005-11-15
申请人： Ho-Ming Leung , Nasima Parveen , Ka-Shu Ko
发明人： Ho-Ming Leung , Nasima Parveen , Ka-Shu Ko
IPC分类号： H03D3/24
CPC分类号： H03L7/113 , H03L7/107 , H03L7/1075 , H04L7/033
摘要： An apparatus comprising an oscillator circuit, a control circuit, a counter circuit and a detector circuit. The oscillator circuit may be configured to generate an output signal oscillating at a particular frequency in response to a control signal. The control circuit may be configured to generate the control signal in response to a first error signal and a second error signal. The counter circuit may be configured to generate the first error signal in response to the output signal and an input signal. The detector circuit may be configured to generate the second error signal in response to the output signal and the input signal.
摘要翻译：一种包括振荡器电路，控制电路，计数器电路和检测器电路的装置。振荡器电路可以被配置为响应于控制信号而产生以特定频率振荡的输出信号。控制电路可以被配置为响应于第一误差信号和第二误差信号而产生控制信号。计数器电路可以被配置为响应于输出信号和输入信号产生第一误差信号。检测器电路可以被配置为响应于输出信号和输入信号而产生第二误差信号。

3. 发明授权

US07769166B2 Dual mode AES implementation to support single and multiple AES operations 有权
标题翻译：双模AES实现，支持单AES和多AES操作
公开(公告)号：US07769166B2
公开(公告)日：2010-08-03
申请号：US11509361
申请日：2006-08-24
申请人： Nasima Parveen , Venkatesh Balasubramanian
发明人： Nasima Parveen , Venkatesh Balasubramanian
IPC分类号： H04L9/32 , H04L9/08 , H04K1/00 , H04K1/04 , G06F1/00 , G06F7/72
CPC分类号： G09C1/00 , H04L9/0631 , H04L9/0637 , H04L2209/12
摘要： An apparatus comprising a mode circuit and an encryption circuit. The mode circuit may be configured to selectively provide register input data on an output signal when in a first mode and memory data on the output signal when in a second mode. The encryption circuit may be configured to interchangeably encrypt/decrypt between the register input data and the memory data.
摘要翻译：一种包括模式电路和加密电路的装置。模式电路可以被配置为当处于第一模式时在输出信号上选择性地提供寄存器输入数据，并且当处于第二模式时，输出信号上的存储器数据。加密电路可以被配置为在寄存器输入数据和存储器数据之间可互换地加密/解密。

4. 发明授权

US5954789A Quotient digit selection logic for floating point division/square root 失效
标题翻译：用于浮点除法/平方根的商数字选择逻辑
公开(公告)号：US5954789A
公开(公告)日：1999-09-21
申请号：US648410
申请日：1996-05-15
申请人： Robert K. Yu , Nasima Parveen , J. Arjun Prabhu
发明人： Robert K. Yu , Nasima Parveen , J. Arjun Prabhu
IPC分类号： G06F7/537 , G06F7/00 , G06F7/483 , G06F7/506 , G06F7/52 , G06F7/535 , G06F7/552 , G06F7/76 , G06F7/38
CPC分类号： G06F7/535 , G06F7/5525 , G06F7/4873 , G06F7/49952
摘要： Quotient digit selection logic is modified so as to prevent a partial remainder equal to the negative divisor from occurring. An enhanced quotient digit selection function prevents the working partial remainder from becoming negative if the result is exact, choosing a quotient digit of zero instead of a quotient digit of one when the actual partial remainder is zero. Using a five bit estimated partial remainder where the upper four bits are zero, a possible carry propagation into fourth most significant bit is detected. This can be accomplished by looking at the fifth most significant sum and carry bits of the redundant partial remainder. If they are both zero, then a carry propagation out of that bit position into the least significant position of the estimated partial remainder is not possible, and a quotient digit of zero is chosen. This provides a one cycle savings since negative partial remainders no longer need to be restored before calculating the sticky bit. Extra hardware is eliminated because it is no longer necessary to provide any extra mechanism for restoring the preliminary final partial remainder. Latency is improved because no additional cycle time is required to restore negative preliminary partial remainders. In an alternative embodiment, where the upper four bits of the estimated partial remainder are ones while the fifth most significant bit is zero, a quotient digit of negative one is chosen. This alternative embodiment allows correct exact results in all rounding modes including rounding toward plus or minus infinity.
摘要翻译：修改商数字选择逻辑，以防止等于负除数的部分余数发生。如果结果是精确的，增强的商数选择功能可以防止工作部分余数变为否定，当实际部分余数为零时，选择零的商数为零，而不是1的商数。使用五位估计的部分余数，其中高四位为零，检测到第四最高有效位的可能进位传播。这可以通过查看第五最高有效和并且携带冗余部分余数的位来实现。如果它们均为零，则从该位位置进入估计的部分余数的最低有效位置的进位传播是不可能的，并且选择零的商数。这提供了一个周期的节省，因为在计算粘性位之前不再需要恢复负部分余数。额外的硬件被消除，因为不再需要提供任何额外的机制来恢复初步的最终部分剩余。改进了延迟，因为不需要额外的周期时间来恢复负的初步部分余数。在替代实施例中，其中估计的部分余数的高四位是1，而第五最高有效位为零，则选择负数的商数。该替代实施例允许在所有舍入模式中的正确精确结果，包括向正或负无穷大舍入。

5. 发明申请

US20190384603A1 PROACTIVE DI/DT VOLTAGE DROOP MITIGATION 审中-公开
公开(公告)号：US20190384603A1
公开(公告)日：2019-12-19
申请号：US16557187
申请日：2019-08-30
申请人： Jason Seung-Min Kim , Nitin N. Garegrat , Anitha Loke , Nasima Parveen , David Y. Fang , Kursad Kiziloglu , Dmitry Sergeyevich Lukiyanchenko , Fabrice Paillet , Andrew Yang
发明人： Jason Seung-Min Kim , Nitin N. Garegrat , Anitha Loke , Nasima Parveen , David Y. Fang , Kursad Kiziloglu , Dmitry Sergeyevich Lukiyanchenko , Fabrice Paillet , Andrew Yang
IPC分类号： G06F9/30
摘要： Embodiments include a method comprising identifying, by an instruction scheduler of a processor core, a first high power instruction in an instruction stream to be executed by an execution unit of the processor core. A pre-charge signal is asserted indicating that the first high power instruction is scheduled for execution. Subsequent to the pre-charge signal being asserted, a voltage boost signal is asserted to cause a supply voltage for the execution unit to be increased. A busy signal indicating that the first high power instruction is executing is received from the execution unit. Based at least in part on the busy signal being asserted, de-asserting the voltage boost signal. More specific embodiments include decreasing the supply voltage for the execution unit subsequent to the de-asserting the voltage boost signal. More Further embodiments include delaying asserting the voltage boost signal based on a start delay time.

6. 发明申请

US20080069339A1 Dual mode AES implementation to support single and multiple AES operations 有权
标题翻译：双模AES实现，支持单AES和多AES操作
公开(公告)号：US20080069339A1
公开(公告)日：2008-03-20
申请号：US11509361
申请日：2006-08-24
申请人： Nasima Parveen , Venkatesh Balasubramanian
发明人： Nasima Parveen , Venkatesh Balasubramanian
IPC分类号： H04L9/28
CPC分类号： G09C1/00 , H04L9/0631 , H04L9/0637 , H04L2209/12
摘要： An apparatus comprising a mode circuit and an encryption circuit. The mode circuit may be configured to selectively provide register input data on an output signal when in a first mode and memory data on the output signal when in a second mode. The encryption circuit may be configured to interchangeably encrypt/decrypt between the register input data and the memory data.
摘要翻译：一种包括模式电路和加密电路的装置。模式电路可以被配置为当处于第一模式时在输出信号上选择性地提供寄存器输入数据，并且当处于第二模式时，输出信号上的存储器数据。加密电路可以被配置为在寄存器输入数据和存储器数据之间可互换地加密/解密。

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