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1. 发明申请

US20110022759A1 MULTIPROCESSOR SYSTEM 有权
标题翻译：多处理器系统
公开(公告)号：US20110022759A1
公开(公告)日：2011-01-27
申请号：US12872423
申请日：2010-08-31
申请人： Hirokazu TAKATA , Naoto Sugai
发明人： Hirokazu TAKATA , Naoto Sugai
IPC分类号： G06F13/26
CPC分类号： G06F13/24
摘要： The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.
摘要翻译：本发明提供一种能够处理在不同处理器中共享一个中断请求的多个中断原因的技术。当通知多个中断原因共享的中断请求时，中断控制器输出中断请求。中断控制器输出的中断请求被其中一个处理器接受。接受中断请求的处理器确定是否发生了处理器必须处理的中断，在发生这样的中断原因时执行中断处理，并且将处理另一中断原因的中断请求通知给另一处理器当相关中断原因未发生时，中断会导致共享中断请求。

2. 发明授权

US07805555B2 Multiprocessor system 失效
标题翻译：多处理器系统
公开(公告)号：US07805555B2
公开(公告)日：2010-09-28
申请号：US12007838
申请日：2008-01-16
申请人： Hirokazu Takata , Naoto Sugai
发明人： Hirokazu Takata , Naoto Sugai
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.
摘要翻译：本发明提供一种能够处理在不同处理器中共享一个中断请求的多个中断原因的技术。当通知多个中断原因共享的中断请求时，中断控制器输出中断请求。中断控制器输出的中断请求被其中一个处理器接受。接受中断请求的处理器确定是否发生了处理器必须处理的中断，在发生这样的中断原因时执行中断处理，并且将处理另一中断原因的中断请求通知给另一处理器当相关中断原因未发生时，中断会导致共享中断请求。

3. 发明申请

US20080172511A1 Multiprocessor system 失效
标题翻译：多处理器系统
公开(公告)号：US20080172511A1
公开(公告)日：2008-07-17
申请号：US12007838
申请日：2008-01-16
申请人： Hirokazu Takata , Naoto Sugai
发明人： Hirokazu Takata , Naoto Sugai
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.
摘要翻译：本发明提供一种能够处理在不同处理器中共享一个中断请求的多个中断原因的技术。当通知多个中断原因共享的中断请求时，中断控制器输出中断请求。中断控制器输出的中断请求被其中一个处理器接受。接受中断请求的处理器确定是否发生了处理器必须处理的中断，在发生这样的中断原因时执行中断处理，并且将处理另一中断原因的中断请求通知给另一处理器当相关中断原因未发生时，中断会导致共享中断请求。

4. 发明授权

US08051234B2 Multiprocessor system 有权
标题翻译：多处理器系统
公开(公告)号：US08051234B2
公开(公告)日：2011-11-01
申请号：US12872423
申请日：2010-08-31
申请人： Hirokazu Takata , Naoto Sugai
发明人： Hirokazu Takata , Naoto Sugai
IPC分类号： G06F13/24
CPC分类号： G06F13/24
摘要： The present invention provides a technique capable of processing a plurality of interrupt causes sharing one interrupt request in different processors. An interrupt controller outputs an interrupt request when the interrupt request shared by a plurality of interrupt causes is notified. The interrupt request output by the interrupt controller is accepted by one of the processors. The processor accepting the interrupt request determines whether the interrupt cause that the processor must process has occurred, executes an interrupt processing when such interrupt cause has occurred, and notifies the generation of the interrupt request to another processor that processes another interrupt cause of the plurality of interrupt causes sharing the interrupt request when the relevant interrupt cause has not occurred.
摘要翻译：本发明提供一种能够处理在不同处理器中共享一个中断请求的多个中断原因的技术。当通知多个中断原因共享的中断请求时，中断控制器输出中断请求。中断控制器输出的中断请求被其中一个处理器接受。接受中断请求的处理器确定是否发生了处理器必须处理的中断，在发生这样的中断原因时执行中断处理，并且将处理另一中断原因的中断请求通知给另一处理器当相关中断原因未发生时，中断会导致共享中断请求。

5. 发明授权

US06795890B1 Data storage method, and data processing device using an erasure block buffer and write buffer for writing and erasing data in memory 失效
标题翻译：数据存储方法和使用擦除块缓冲器和写入缓冲器的数据处理装置，用于在存储器中写入和擦除数据
公开(公告)号：US06795890B1
公开(公告)日：2004-09-21
申请号：US09640454
申请日：2000-08-17
申请人： Naoto Sugai , Atsushi Settsu , Saburo Kobayashi
发明人： Naoto Sugai , Atsushi Settsu , Saburo Kobayashi
IPC分类号： G06F1300
CPC分类号： G11C16/105 , G11C16/102
摘要： A data processing device includes flash memory; nonvolatile memory having an erasure block buffer in which there are stored data recorded in an erasure-unit region of the flash memory; a write control controller for writing into the erasure block buffer write request data, which are to be written into the flash memory; a save unit for saving non-changing data stored in the flash memory to the erasure block buffer; an erasure instruction unit for instructing erasure of the data from the flash memory; and a write unit for writing the data recorded in the erasure block buffer to the flash memory.
摘要翻译：数据处理装置包括闪存; 具有擦除块缓冲器的非易失性存储器，其中存储有记录在闪速存储器的擦除单元区域中的数据; 写入控制器，用于写入擦除块缓冲器写入请求数据，写入到闪存中; 保存单元，用于将存储在闪存中的不变数据保存到擦除块缓冲器; 擦除指令单元，用于指示擦除来自闪速存储器的数据; 以及写入单元，用于将记录在擦除块缓冲器中的数据写入闪速存储器。

6. 发明授权

US06571312B1 Data storage method and data processing device using an erasure block buffer and write buffer for writing and erasing data in memory 有权
标题翻译：使用擦除块缓冲器和写入缓冲器的数据存储方法和数据处理装置，用于在存储器中写入和擦除数据
公开(公告)号：US06571312B1
公开(公告)日：2003-05-27
申请号：US09504713
申请日：2000-02-16
申请人： Naoto Sugai , Atsushi Settsu , Saburo Kobayashi
发明人： Naoto Sugai , Atsushi Settsu , Saburo Kobayashi
IPC分类号： G06F1300
CPC分类号： G11C16/16
摘要： A data processing device includes flash memory 101; nonvolatile memory 102 having an erasure block buffer 103 in which there are stored data recorded in an erasure-unit region of the flash memory 101; a write controller 111 for writing into the erasure block buffer 103 write request data which are to be written into the flash memory 101; a save unit 112 for saving non-changing data stored in the flash memory 101 to the erasure block buffer 103; an erasure instruction unit 301 for instructing erasure of the data from the erasure-unit region of flash memory 101; and a write unit for writing the data recorded in the erasure block buffer 103 to the flash memory 101. A comparison may be made between the erasure unit regions into which first and second write data are to be written. The data processing device may further include a write buffer for storing write data.
摘要翻译：数据处理装置包括闪存101; 具有擦除块缓冲器103的非易失性存储器102，其中存储有记录在闪速存储器101的擦除单元区域中的数据; 写入控制器111，用于写入擦除块缓冲器103写入要写入闪存101的请求数据; 保存单元112，用于将存储在闪速存储器101中的不变数据保存到擦除块缓冲器103; 用于指示擦除来自闪存101的擦除单元区域的数据的擦除指令单元301; 以及用于将记录在擦除块缓冲器103中的数据写入闪速存储器101的写入单元。可以在要写入第一和第二写入数据的擦除单元区域之间进行比较。数据处理装置还可以包括用于存储写入数据的写入缓冲器。

7. 发明授权

US06374353B1 Information processing apparatus method of booting information processing apparatus at a high speed 失效
标题翻译：以高速启动信息处理装置的信息处理装置方法
公开(公告)号：US06374353B1
公开(公告)日：2002-04-16
申请号：US09261255
申请日：1999-03-03
申请人： Atsushi Settsu , Noriyuki Baba , Naoto Sugai
发明人： Atsushi Settsu , Noriyuki Baba , Naoto Sugai
IPC分类号： G06F9445
CPC分类号： G06F9/4406
摘要： A method of booting up an information processing apparatus is provided. An operating system is divided into a mini operating system (OS) module having a function of bootstrap and an OS main body module having functions other than the function of bootstrap. The mini OS module can be located in a boot block of a boot device, whereas the OS main body module can be located in a file system of the boot device. A firmware or F/W code module stored in a ROM loads the mini OS module into memory when booting up the information processing apparatus. The mini OS module then loads the OS main body module into memory and then initializes the OS main body module.
摘要翻译：提供了引导信息处理装置的方法。操作系统被分为具有引导功能的微型操作系统（OS）模块和具有除引导功能之外的功能的OS主体模块。 mini OS模块可以位于引导设备的引导块中，而OS主体模块可以位于引导设备的文件系统中。存储在ROM中的固件或F / W代码模块在启动信息处理设备时将mini OS模块加载到存储器中。然后，微型操作系统模块将OS主体模块加载到存储器中，然后初始化OS主体模块。

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