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1. 发明授权

US5434813A Semiconductor memory device and manufacturing method of the same 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US5434813A
公开(公告)日：1995-07-18
申请号：US114274
申请日：1993-08-31
申请人： Katsuhiko Tamura , Yukari Imai , Naoko Otani
发明人： Katsuhiko Tamura , Yukari Imai , Naoko Otani
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792 , H01L27/10
CPC分类号： H01L29/66825 , H01L29/511 , H01L27/115 , Y10S438/981
摘要： A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.
摘要翻译：半导体存储器件有效地防止了在数据写入和擦除操作中电子移动的区域上形成栅极鸟喙氧化物膜。在半导体存储器件中，在漏极杂质扩散层和源极杂质扩散层上形成厚度大于第一栅极氧化物膜的氮化物膜以围绕第一栅极氧化物膜。浮栅电极具有突出在氮化物膜上的相对端。

2. 发明授权

US5633184A Method of making semiconductor device with floating bate 失效
标题翻译：制造半导体器件的浮动形式的方法
公开(公告)号：US5633184A
公开(公告)日：1997-05-27
申请号：US386367
申请日：1995-02-09
申请人： Katsuhiko Tamura , Yukari Imai , Naoko Otani
发明人： Katsuhiko Tamura , Yukari Imai , Naoko Otani
IPC分类号： H01L21/8247 , H01L21/336 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792 , H01C21/8247 , H01C21/265
CPC分类号： H01L29/66825 , H01L29/511 , H01L27/115 , Y10S438/981
摘要： A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.
摘要翻译：半导体存储器件有效地防止了在数据写入和擦除操作中电子移动的区域上形成栅极鸟喙氧化物膜。在半导体存储器件中，在漏极杂质扩散层和源极杂质扩散层上形成厚度大于第一栅极氧化物膜的氮化物膜以围绕第一栅极氧化物膜。浮栅电极具有突出在氮化物膜上的相对端。

3. 发明授权

US5786612A Semiconductor device comprising trench EEPROM 失效
标题翻译：半导体器件包括沟槽EEPROM
公开(公告)号：US5786612A
公开(公告)日：1998-07-28
申请号：US633093
申请日：1996-04-16
申请人： Naoko Otani , Toshiharu Katayama
发明人： Naoko Otani , Toshiharu Katayama
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , H01L27/115
摘要： Each of source regions (4) is provided only immediately below a bottom surface (3B) of each of trenches (3) which is formed in a silicon substrate (1), extending inward from a main surface (1S) thereof along a second direction, and each of gate electrode portions (23) is provided inside each of the trenches (3). Specifically, each of the gate electrode portions (23) consists of a gate oxide film (19) formed on a side surface (S1) and part of the bottom surface (3B) of the trench (3), an FG electrode (20) formed thereon, a gate insulating film (21) formed on a side surface of the FG electrode (20) which is out of contact with the gate oxide film (19), an upper surface of the FG electrode (20), a side surface (2S) and the other part of the bottom (3B) of the trench (3), and a CG electrode (22) formed so as to cover an upper surface of the gate insulating film (21). Each of drain regions (11) is shared by the two adjacent transistors. The device configuration as above achieves reduction in area of the gate electrode portions (23) and further reduction in each level difference between both regions having and not having the gate electrode portion (23). Thus, reduction in level difference of each memory cell is achieved while reduction in area of each memory cell is ensured.
摘要翻译：每个源极区域（4）仅设置在形成在硅衬底（1）中的每个沟槽（3）的底表面（3B）的正下方，从其主表面（1S）向内沿着第二方向并且每个沟槽（3）内设置有栅电极部（23）。具体而言，各栅电极部（23）由形成在沟槽（3）的侧面（S1）和底面（3B）的一部分的栅极氧化膜（19），FG电极（20）形成在与栅极氧化膜（19）不接触的FG电极（20）的侧面上的栅极绝缘膜（21），FG电极（20）的上表面，侧面（2S）和沟槽（3）的底部（3B）的另一部分，以及形成为覆盖栅极绝缘膜（21）的上表面的CG电极（22）。漏极区域（11）中的每一个由两个相邻的晶体管共享。如上所述的器件结构实现了栅电极部分（23）的面积减小，并且进一步减小了具有栅极电极部分（23）的两个区域之间的每个电平差。因此，在确保每个存储单元的面积减小的同时，实现每个存储单元的电平差的减小。

4. 发明授权

US5708285A Non-volatile semiconductor information storage device 失效
标题翻译：非易失性半导体信息存储装置
公开(公告)号：US5708285A
公开(公告)日：1998-01-13
申请号：US526391
申请日：1995-09-11
申请人： Naoko Otani , Toshiharu Katayama
发明人： Naoko Otani , Toshiharu Katayama
IPC分类号： G11C11/56 , G11C16/04 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11517 , G11C11/5621 , G11C16/0458 , H01L27/115 , H01L29/7887 , G11C2211/5612
摘要： A non-volatile semiconductor storage device with which a multi-value memory is realized and the amount of information storable is increased without increasing the number of memory transistors and the area occupied thereby. A gate electrode portion 20a of each memory transistor has a two-layer floating gate structure comprising two floating gate electrodes 22a, 22b and a control gate electrode 24 which are substantially vertically laminated one above another. The non-volatile semiconductor storage device is thereby constructed as a multi-value memory capable of providing a state "1" where electrons are injected into the first floating gate electrode 22a, a state "0" where electrons are injected into the first and second floating gate electrodes 22a, 22b, and a state "2" where electrons are withdrawn from the first and second floating gate electrodes 22a, 22b.
摘要翻译：实现多值存储器的非易失性半导体存储装置，并且不增加存储晶体管的数量和由此占用的面积来增加可存储的信息量。每个存储晶体管的栅电极部分20a具有两层浮栅结构，包括两个浮置栅电极22a，22b和控制栅电极24，它们基本上垂直层叠在另一个上。因此，非易失性半导体存储装置被构造为能够提供电子注入到第一浮栅电极22a中的状态“1”的多值存储器，其中电子注入第一和第二浮动栅电极22a的状态“0” 浮栅电极22a，22b和电子从第一和第二浮栅22a，22b取出的状态“2”。

5. 发明授权

US5677204A Method of evaluating a thin film for use in semiconductor device 失效
标题翻译：半导体装置用薄膜评价方法
公开(公告)号：US5677204A
公开(公告)日：1997-10-14
申请号：US630211
申请日：1996-04-10
申请人： Yukari Imai , Toshiharu Katayama , Naoko Otani
发明人： Yukari Imai , Toshiharu Katayama , Naoko Otani
IPC分类号： G01N21/88 , G01N21/956 , H01L21/3063 , H01L21/321 , H01L21/66 , H01L21/8238 , H01L21/8242 , H01L21/8247 , H01L27/108 , H01L29/788 , H01L29/792 , G01R31/26 , H01L21/306 , H01L21/479
CPC分类号： H01L27/1085 , H01L21/32105 , H01L21/823878 , H01L27/11517
摘要： A semiconductor device (100) including a silicon substrate (1), a gate oxide film (2) formed on the silicon substrate (1) and having a defect (3) and a dielectric breakdown voltage failure portion (4), and a polysilicon film (5) formed on the gate oxide film (2) is immersed in a chemical etchant (7) in a wet etching apparatus (9). With the silicon substrate (1) serving as an anode, a DC voltage source (6) of the wet etching apparatus (9) applies voltage to the silicon substrate (1) to perform anode oxidation. Passivation layers (10) are formed on parts of the surface of the polysilicon film (5) which overlies the defect (3) and dielectric breakdown voltage failure portion (4) but are not formed on the surface of the polysilicon film (5) in regions insulated by the gate oxide film (2). The polysilicon film (5) in the regions on which the passivation layers (10) are not formed is removed by the chemical etchant (7).
摘要翻译：一种半导体器件（100），包括硅衬底（1），形成在硅衬底（1）上并具有缺陷（3）和介电击穿电压失效部分（4）的栅极氧化膜（2）形成在栅极氧化膜（2）上的膜（5）在湿式蚀刻装置（9）中浸渍在化学蚀刻剂（7）中。在硅衬底（1）用作阳极的情况下，湿蚀刻装置（9）的直流电压源（6）向硅衬底（1）施加电压以进行阳极氧化。钝化层（10）形成在多晶硅膜（5）的覆盖缺陷（3）和绝缘击穿电压失效部分（4）但不形成在多晶硅膜（5）的表面上的部分上，由栅氧化膜（2）绝缘的区域。通过化学蚀刻剂（7）除去未形成有钝化层（10）的区域中的多晶硅膜（5）。

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