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1. 发明申请

US20060250523A1 Video signal processing apparatus 审中-公开
标题翻译：视频信号处理装置
公开(公告)号：US20060250523A1
公开(公告)日：2006-11-09
申请号：US11357094
申请日：2006-02-21
申请人： Naoki Kuwajima , Takayoshi Mogi , Hiroshi Azami , Takashi Asano , Shota Kida , Kazuyuki Rikiishi , Masakazu Nakamura
发明人： Naoki Kuwajima , Takayoshi Mogi , Hiroshi Azami , Takashi Asano , Shota Kida , Kazuyuki Rikiishi , Masakazu Nakamura
IPC分类号： H04N5/44
CPC分类号： H04N5/64 , G06F1/1601 , G06F1/1605 , G06F2200/1612 , G06F2200/1631 , G11B33/10 , G11B33/12 , H04N5/4401
摘要： According to one embodiment, there is provided a video signal processing apparatus including an apparatus main body which performs predetermined signal processing to a received video signal to display the video signal and a stand which is placed on a predetermined base and supports the apparatus main body to upright stand a video display screen, the stand having an HDD to be connected to a signal processing unit in the apparatus main body to enable to transmit the video signal between the HDD and the signal processing unit.
摘要翻译：根据一个实施例，提供了一种视频信号处理装置，其包括对接收到的视频信号执行预定信号处理以显示视频信号的装置主体和放置在预定基座上并支撑设备主体的支架直立站在视频显示屏幕上，支架具有要连接到设备主体中的信号处理单元的HDD，以便能够在HDD和信号处理单元之间传输视频信号。

2. 发明授权

US07701268B2 Clock generation circuit 失效
标题翻译：时钟发生电路
公开(公告)号：US07701268B2
公开(公告)日：2010-04-20
申请号：US11706421
申请日：2007-02-15
申请人： Naoki Kuwajima
发明人： Naoki Kuwajima
IPC分类号： H03L7/06
CPC分类号： G06F1/04
摘要： In a second system that generates a clock signal that is synchronized with a first system, a control voltage value that controls the second oscillator such that the second system is synchronized with the first system is monitored according to the phase difference between a reference signal that is generated using the output of a first oscillator in the first system and the output of a second oscillator, whereby frequency fluctuation that occurs due to age deterioration of the first oscillator is detected.
摘要翻译：在产生与第一系统同步的时钟信号的第二系统中，控制第二振荡器的控制电压值，使得第二系统与第一系统同步，根据参考信号使用第一系统中的第一振荡器的输出和第二振荡器的输出产生，由此检测由于第一振荡器的老化劣化而发生的频率波动。

3. 发明申请

US20060262232A1 Video image signal processing apparatus 审中-公开
标题翻译：视频图像信号处理装置
公开(公告)号：US20060262232A1
公开(公告)日：2006-11-23
申请号：US11409986
申请日：2006-04-25
申请人： Naoki Kuwajima , Kazuyuki Rikiishi , Takayoshi Mogi , Hiroshi Azami , Takashi Asano , Shota Kida , Masakazu Nakamura
发明人： Naoki Kuwajima , Kazuyuki Rikiishi , Takayoshi Mogi , Hiroshi Azami , Takashi Asano , Shota Kida , Masakazu Nakamura
IPC分类号： G06F1/16 , H04N5/64
CPC分类号： G06F1/1601 , G06F1/181 , H04N5/64 , H04N5/76 , H04N5/781
摘要： According to one embodiment, a video image signal processing apparatus includes a device main body which displays a video image that corresponds to a received video image signal, an HDD unit having formed therein an operating piece elastically deformed to enable a push operation of an operating component, a stand supporting the device main body while a video image display screen is erected, and having a housing section which removably houses the HDD unit, and also having an operator which elastically deforms the operating piece at a position opposed to the operating piece of the HDD unit to make the operating component operable.
摘要翻译：根据一个实施例，视频图像信号处理装置包括显示对应于接收的视频图像信号的视频图像的设备主体，其中形成有弹性变形的操作片的HDD单元，以使得操作部件在支撑视频图像显示屏幕的同时支撑设备主体的支架，以及具有可移除地容纳HDD单元的壳体部分，并且还具有使操作件在与操作件的操作件相对的位置处弹性变形的操作者 HDD单元，使操作组件可操作。

4. 发明授权

US5459764A Clock synchronization system 失效
标题翻译：时钟同步系统
公开(公告)号：US5459764A
公开(公告)日：1995-10-17
申请号：US326831
申请日：1994-10-21
申请人： Naoto Ohgami , Naoki Kuwajima
发明人： Naoto Ohgami , Naoki Kuwajima
IPC分类号： H04L1/22 , H04J3/06 , H04L7/00 , H04L7/02
CPC分类号： H04J3/0688
摘要： A clock synchronization system is constituted by first and second clock generating sections. The first and second clock generating units are alternately set in current and spare use modes. The apparatus clock from one clock generating section in the current use mode is supplied to an external circuit. In each clock generating section, a state signal generating section receives a first state signal representing one of the modes, and outputs a second state signal representing a set mode opposite to the mode represented by the first state signal to the other clock generating section. A clock generating section generates a clock synchronized with the network sync signal. A frequency-dividing circuit outputs an apparatus clock by frequency-dividing the clock in synchronism with the network sync signal when the first state signal represents the spare unit mode, and outputs an apparatus clock by frequency-dividing the clock in synchronism with a sync pulse from the clock generating section when the first state signal represents the current use mode. A clock control section outputs an apparatus clock from the frequency-dividing circuit as a supply clock only when the second state signal represents the current use mode. A sync pulse generating circuit generates a sync pulse which is advances by a predetermined time.
摘要翻译：时钟同步系统由第一和第二时钟产生部分构成。第一和第二时钟发生单元交替地设置为当前和备用模式。来自当前使用模式的一个时钟发生部分的装置时钟被提供给外部电路。在每个时钟产生部分中，状态信号产生部分接收表示其中一个模式的第一状态信号，并将表示与由第一状态信号表示的模式相反的设置模式的第二状态信号输出到另一时钟产生部分。时钟产生部分产生与网络同步信号同步的时钟。当第一状态信号表示备用单元模式时，分频电路通过与网络同步信号同步地对时钟进行分频而输出设备时钟，并且通过与同步脉冲同步地对时钟进行分频来输出设备时钟当第一状态信号表示当前使用模式时，从时钟产生部分。时钟控制部分仅在第二状态信号表示当前使用模式时从分频电路输出装置时钟作为供给时钟。同步脉冲发生电路产生预定时间前进的同步脉冲。

5. 发明申请

US20060198097A1 Video signal processing apparatus 审中-公开
标题翻译：视频信号处理装置
公开(公告)号：US20060198097A1
公开(公告)日：2006-09-07
申请号：US11357190
申请日：2006-02-21
申请人： Naoki Kuwajima , Takayoshi Mogi , Hiroshi Azami , Takashi Asano , Shota Kida , Kazuyuki Rikiishi , Masakazu Nakamura
发明人： Naoki Kuwajima , Takayoshi Mogi , Hiroshi Azami , Takashi Asano , Shota Kida , Kazuyuki Rikiishi , Masakazu Nakamura
IPC分类号： G06F1/16
CPC分类号： H04N21/4147 , H04N5/775 , H04N5/781 , H04N21/42669
摘要： According to one embodiment, there is provided a video signal processing apparatus including an apparatus main body which performs predetermined signal processing to a received video signal to display the video signal, an HDD unit which incorporates an HDD therein, and a stand which is placed on a predetermined base and supports the apparatus main body so as to upright stand a video display screen, the stand having a storing unit which attachably/detachably stores the HDD unit in the stand.
摘要翻译：根据一个实施例，提供了一种视频信号处理设备，包括：对接收到的视频信号执行预定信号处理以显示视频信号的装置主体，包含HDD的HDD单元和放置在其上的支架一个预定的底座并且支撑设备主体以便立式地架在视频显示屏幕上，该支架具有一个可将可拆卸地将HDD单元存储在支架中的存储单元。

6. 发明授权

US06801093B2 Frequency synchronous apparatus and frequency synchronous control method 失效
标题翻译：频率同步装置和频率同步控制方法
公开(公告)号：US06801093B2
公开(公告)日：2004-10-05
申请号：US10153648
申请日：2002-05-24
申请人： Naoki Kuwajima
发明人： Naoki Kuwajima
IPC分类号： H03L700
CPC分类号： H03L7/093 , H03L7/105 , H03L7/18
摘要： A frequency synchronous apparatus includes a switch, frequency division circuit, phase comparison circuit, frequency adjustment and calculation circuit, memory, conversion circuit, and voltage-controlled oscillator. The switch selects either one of a highly stable clock output and a reference clock output in accordance with a mode switching signal. The frequency division circuit divides the frequency of the synchronous clock. The phase comparison circuit detects the phase difference between an output clock from the frequency division circuit and an output clock from the switch, and outputs a phase difference value. The frequency adjustment and calculation circuit performs synchronous control so as to adjust the phase difference value output from the phase comparison circuit to 0, and outputs a synchronous control value at this time. The memory holds the synchronous control value output from the frequency adjustment and calculation circuit. The conversion circuit converts the synchronous control value into a control voltage value. The voltage-controlled oscillator outputs a synchronous clock on the basis of the control voltage value. The present invention also provides a frequency synchronous control method.
摘要翻译：频率同步装置包括开关，分频电路，相位比较电路，频率调整和计算电路，存储器，转换电路和压控振荡器。该开关根据模式切换信号选择高度稳定的时钟输出和参考时钟输出之一。分频电路分频同步时钟的频率。相位比较电路检测来自分频电路的输出时钟与来自开关的输出时钟之间的相位差，并输出相位差值。频率调整和计算电路执行同步控制，以将从相位比较电路输出的相位差值调整为0，此时输出同步控制值。存储器保持从频率调整和计算电路输出的同步控制值。转换电路将同步控制值转换为控制电压值。压控振荡器根据控制电压值输出同步时钟。本发明还提供一种频率同步控制方法。

7. 发明申请

US20070210849A1 Clock generation circuit 失效
标题翻译：时钟发生电路
公开(公告)号：US20070210849A1
公开(公告)日：2007-09-13
申请号：US11706421
申请日：2007-02-15
申请人： Naoki Kuwajima
发明人： Naoki Kuwajima
IPC分类号： G06F1/04
CPC分类号： G06F1/04
摘要： In a second system that generates a clock signal that is synchronized with a first system, a control voltage value that controls the second oscillator such that the second system is synchronized with the first system is monitored according to the phase difference between a reference signal that is generated using the output of a first oscillator in the first system and the output of a second oscillator, whereby frequency fluctuation that occurs due to age deterioration of the first oscillator is detected.
摘要翻译：在产生与第一系统同步的时钟信号的第二系统中，控制第二振荡器的控制电压值，使得第二系统与第一系统同步，根据参考信号使用第一系统中的第一振荡器的输出和第二振荡器的输出产生，由此检测由于第一振荡器的老化劣化而发生的频率波动。

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