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1. 发明专利

JP2004017261A Machining device, machining method, and machining system 审中-公开
公开(公告)号：JP2004017261A
公开(公告)日：2004-01-22
申请号：JP2002179739
申请日：2002-06-20
申请人： Takanori Kubo , Toshikatsu Nakajima , Naohiro Nishikawa , Shinya Tsukamoto , 中島利勝 , 久保孝典 , 塚本真也 , 西川尚宏
发明人： TSUKAMOTO SHINYA , NISHIKAWA NAOHIRO , KUBO TAKANORI , NAKAJIMA TOSHIKATSU
IPC分类号： B23P25/00
摘要： PROBLEM TO BE SOLVED: To provide a machining device, a machining method, and a machining system, wherein machining is performed without using processing liquid such as non-watersoluble working liquid and watersoluble working liquid.
SOLUTION: This machining device comprises: a tool such as a grind stone 8 for machining a conductive workpiece 9; a working liquid supplying nozzle 4 for supplying water 10 as working liquid to the workpiece 9 at the time of machining with a tool; and an anode part and a cathode part for flowing current to the workpiece 9. A processing liquid supplying nozzle 4 is used as the anode part, and a center 7 is used as the cathode part. The anode part and the cathode part are electrically connected with an anode and a cathode of a direct current power source supply/control device 1.
COPYRIGHT: (C)2004,JPO

2. 发明授权

US08166482B2 Scheduling method, scheduling apparatus and multiprocessor system 有权
标题翻译：调度方法，调度设备和多处理器系统
公开(公告)号：US08166482B2
公开(公告)日：2012-04-24
申请号：US13012054
申请日：2011-01-24
申请人： Naohiro Nishikawa
发明人： Naohiro Nishikawa
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： A thread status managing unit organizes a plurality of threads into groups and manages the status of the thread groups. A ready queue queues thread groups in a ready state or a running state in the order of priority and, within the same priority level, in the FIFO order. An assignment list generating unit sequentially retrieves the thread groups from the ready queue. The assignment list appends a retrieved thread group to a thread assignment list only when all threads belonging to the retrieved thread group are assignable to the respective processors at the same time. A thread assigning unit assigns all threads belonging to the thread groups stored in the thread assignment list to the respective processors.
摘要翻译：线程状态管理单元将多个线程组织成组并管理线程组的状态。准备好的队列将处于就绪状态或运行状态的线程组以优先级顺序排队，并且在同一优先级别内以FIFO顺序排队。分配表生成单元从就绪队列顺序地检索线程组。只有当属于检索到的线程组的所有线程可以同时分配给相应的处理器时，分配列表将检索到的线程组添加到线程分配列表。线程分配单元将属于线程分配列表中存储的线程组的所有线程分配给各个处理器。

3. 发明申请

US20110042719A1 SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20110042719A1
公开(公告)日：2011-02-24
申请号：US12933340
申请日：2009-03-18
申请人： Hiroyuki Sazawa , Naohiro Nishikawa , Yasuyukl Kurita , Masahiko Hata
发明人： Hiroyuki Sazawa , Naohiro Nishikawa , Yasuyukl Kurita , Masahiko Hata
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7787 , H01L23/291 , H01L23/3171 , H01L29/1066 , H01L29/2003 , H01L29/517 , H01L29/518 , H01L29/66462 , H01L2924/0002 , H01L2924/00
摘要： It is an objective of the present invention to increase channel current density while allowing a GaN field effect transistor to perform normally-off operation.Provided is a a semiconductor device comprising a group 3-5 compound semiconductor channel layer including nitrogen; an electron supply layer that has a groove in a surface thereof that is opposite a surface facing the channel layer and that supplies the channel layer with electrons; a p-type semiconductor layer that is formed in the groove of the electron supply layer; and a control electrode formed directly on the p-type semiconductor layer or on an intermediate layer formed on the p-type semiconductor layer.
摘要翻译：本发明的目的是增加沟道电流密度，同时允许GaN场效应晶体管执行常关操作。提供一种半导体器件，其包括含有氮的组3-5化合物半导体沟道层; 电子供给层，其表面中具有与面向沟道层的表面相对的沟槽，并且向沟道层提供电子; 形成在电子供给层的槽内的p型半导体层; 以及直接形成在p型半导体层上或形成在p型半导体层上的中间层上的控制电极。

4. 发明申请

US20100117094A1 GALLIUM NITRIDE EPITAXIAL CRYSTAL, METHOD FOR PRODUCTION THEREOF, AND FIELD EFFECT TRANSISTOR 有权
标题翻译：氮化铝外延晶体，其生产方法和场效应晶体管
公开(公告)号：US20100117094A1
公开(公告)日：2010-05-13
申请号：US12527116
申请日：2008-02-07
申请人： Naohiro Nishikawa , Hiroyuki Sazawa , Masahiko Hata
发明人： Naohiro Nishikawa , Hiroyuki Sazawa , Masahiko Hata
IPC分类号： H01L29/772 , H01L29/205 , H01L21/20
CPC分类号： H01L29/66462 , H01L29/2003 , H01L29/7783
摘要： The present invention provides a gallium nitride type epitaxial crystal, a method for producing the crystal, and a field effect transistor using the crystal. The gallium nitride type epitaxial crystal comprises a base substrate and the following (a) to (e), wherein a connection layer comprising a gallium nitride type crystal is arranged in an opening of the non-gallium nitride type insulating layer to electrically connect the first buffer layer and the p-conductive type semiconductor crystal layer. (a) a gate layer, (b) a high purity first buffer layer containing a channel layer contacting an interface on the base substrate side of the gate layer, (c) a second buffer layer arranged on the base substrate side of the first buffer layer, (d) a non-gallium nitride type insulating layer arranged on the base substrate side of the second buffer layer, and having the opening at a part thereof, and (e) a p-conductive type semiconductor crystal layer arranged on the base substrate side of the insulating layer.
摘要翻译：本发明提供一种氮化镓型外延晶体，该晶体的制造方法以及使用该晶体的场效应晶体管。氮化镓型外延晶体包括基底和以下（a）至（e），其中包括氮化镓型晶体的连接层被布置在非氮化镓型绝缘层的开口中，以将第一缓冲层和p导电型半导体晶体层。（a）栅极层，（b）高纯度第一缓冲层，其含有与栅极层的基底侧上的界面接触的沟道层，（c）第二缓冲层，其设置在第一缓冲层的基底侧层，（d）配置在第二缓冲层的基板侧的非氮化镓系绝缘层，其一部分具有开口部，（e）配置在基板上的p导电型半导体晶体层绝缘层的衬底侧。

5. 发明申请

US20100084742A1 Method for manufacturing semiconductor epitaxial crystal substrate 有权
标题翻译：半导体外延晶体基板的制造方法
公开(公告)号：US20100084742A1
公开(公告)日：2010-04-08
申请号：US12310984
申请日：2007-09-14
申请人： Hiroyuki Sazawa , Naohiro Nishikawa , Masahiko Hata
发明人： Hiroyuki Sazawa , Naohiro Nishikawa , Masahiko Hata
IPC分类号： H01L29/20 , H01L21/20 , H01L21/31 , H01L29/423
CPC分类号： H01L29/66462 , H01L21/02458 , H01L21/0254 , H01L21/0257 , H01L21/0262 , H01L21/31608 , H01L21/31616 , H01L21/31645 , H01L29/2003 , H01L29/517 , H01L29/518 , H01L29/78
摘要： The present invention provides a method for manufacturing a gallium nitride semiconductor epitaxial crystal substrate with a dielectric film which has a low gate leak current and negligibly low gate lag, drain lag, and current collapse characteristics. The method for manufacturing a semiconductor epitaxial crystal substrate is a method for manufacturing a semiconductor epitaxial crystal substrate in which a dielectric layer of a nitride dielectric material or an oxide dielectric material in an amorphous form functioning as a passivation film or a gate insulator is provided on a surface of a nitride semiconductor crystal layer grown by metal organic chemical vapor deposition. In the method, after the nitride semiconductor crystal layer is grown in an epitaxial growth chamber, the dielectric layer is grown on the nitride semiconductor crystal layer in the epitaxial growth chamber.
摘要翻译：本发明提供一种具有电介质膜的氮化镓半导体外延晶体基板的制造方法，所述电介质膜具有低栅极泄漏电流和可忽略的低栅极滞后，漏极滞后和电流塌陷特性。半导体外延晶体基板的制造方法是制造半导体外延晶体基板的方法，其中，作为钝化膜或栅极绝缘体的非晶形式的氮化物电介质材料或氧化物电介质材料的介电层设置在通过金属有机化学气相沉积生长的氮化物半导体晶体层的表面。在该方法中，在外延生长室中生长氮化物半导体晶体层之后，在外延生长室中的氮化物半导体晶体层上生长电介质层。

6. 发明申请

US20070046508A1 Sampling rate converter and a semiconductor integrated circuit 审中-公开
标题翻译：采样率转换器和半导体集成电路
公开(公告)号：US20070046508A1
公开(公告)日：2007-03-01
申请号：US11512171
申请日：2006-08-30
申请人： Naohiro Nishikawa
发明人： Naohiro Nishikawa
IPC分类号： H03M7/00
CPC分类号： G11B20/10 , G11B20/10527 , G11B2020/1062
摘要： The present invention reduces the manufacturing cost of a sampling rate converter. The sampling rate converter disclosed herein comprises a buffer for buffering input data, a sampling rate converter core for converting a sampling rate of data output from the buffer, and a sampling rate conversion control unit capable of controlling sampling rate conversion by the sampling rate converter core. The sampling rate conversion control unit comprises a table of data for control of the sampling rate conversion by the sampling rate converter core and an input sampling rate calculating module which determines an input sampling rate for the sampling rate converter core by referring to the table, wherein the data for control in the table can be updated. A PLL circuit for sampling rate conversion is dispensed with and reducing the manufacturing cost of the sampling converter is achieved.
摘要翻译：本发明降低了采样率变换器的制造成本。本文公开的采样率转换器包括用于缓冲输入数据的缓冲器，用于转换从缓冲器输出的数据的采样率的采样率转换器核心和能够控制采样率转换器核心的采样率转换的采样率转换控制单元。采样率转换控制单元包括用于控制采样率转换器核心的采样率转换的数据表和通过参考该表确定采样率转换器芯的输入采样率的输入采样率计算模块，其中可以更新表中控制的数据。用于采样率转换的PLL电路被省去，并且降低了采样转换器的制造成本。

7. 发明申请

US20090008652A1 Free-Standing Substrate, Method for Producing the Same and Semiconductor Light-Emitting Device 审中-公开
标题翻译：自由基底材，其制造方法和半导体发光装置
公开(公告)号：US20090008652A1
公开(公告)日：2009-01-08
申请号：US11908539
申请日：2006-03-20
申请人： Kazumasa Ueda , Naohiro Nishikawa , Yoshihiko Tsuchida
发明人： Kazumasa Ueda , Naohiro Nishikawa , Yoshihiko Tsuchida
IPC分类号： H01L21/28 , H01L29/12
CPC分类号： C23C16/30 , C30B25/183 , C30B29/403 , H01L21/0237 , H01L21/02488 , H01L21/02513 , H01L21/0254 , H01L21/02573 , H01L21/0262 , H01L21/02639 , H01L21/02642 , H01L21/02647 , H01L33/007
摘要： The present invention provides a free-standing substrate, a method for producing the same and a semiconductor light-emitting device. The free-standing substrate comprises a semiconductor layer and inorganic particles, wherein the inorganic particles are included in the semiconductor layer. The method for producing a free-standing substrate comprises the steps of: (a) placing inorganic particles on a substrate, (b) growing a semiconductor layer thereon, and (c) separating the semiconductor layer from the substrate, in that order. The semiconductor light-emitting device comprises the free-standing substrate, a conductive layer, a light-emitting device, and electrodes.
摘要翻译：本发明提供一种自立式基板，其制造方法和半导体发光装置。独立基板包括半导体层和无机颗粒，其中无机颗粒包括在半导体层中。制造独立基板的方法包括以下步骤：（a）将无机颗粒放置在基板上，（b）在其上生长半导体层，以及（c）依次将半导体层与基板分离。半导体发光器件包括独立的衬底，导电层，发光器件和电极。

8. 发明申请

US20070245218A1 Semiconductor integrated circuit and record player 审中-公开
标题翻译：半导体集成电路和唱机
公开(公告)号：US20070245218A1
公开(公告)日：2007-10-18
申请号：US11699006
申请日：2007-01-29
申请人： Naohiro Nishikawa
发明人： Naohiro Nishikawa
IPC分类号： G11C29/00
CPC分类号： G11B20/10 , G11B20/00007 , G11B20/00086 , G11B27/105 , G11B2020/00014 , G11B2020/10833 , G11B2220/2516 , G11B2220/2545 , G11B2220/41
摘要： The present invention provides a technique capable of performing a process for encoding data read from a first storing medium and writing the encoded data to a second storing medium seemingly at high speed and, moreover, excellently protecting the copyright of the data. A semiconductor integrated circuit includes: a first processor for performing primary encoding on data read from a first storing medium, thereby forming a temporary file in a second storing medium; and a second processor for performing secondary encoding on the temporary file so as to be converted to compressed stream data, thereby enabling the temporary file and the compressed stream data to be reproduced. Reproduction of the data in the second storing medium is enabled on completion of the primary encoding, so that the process for encoding data read from the first storing medium and writing the encoded data to the second storing medium can be performed seemingly at high speed. Since the temporary file is subjected to the primary encoding, the copyright of the data is protected.
摘要翻译：本发明提供了一种能够执行从第一存储介质读取的数据的编码处理，并将编码数据写入高速的第二存储介质，而且极好地保护数据版权的技术。半导体集成电路包括：第一处理器，用于对从第一存储介质读取的数据进行主编码，从而在第二存储介质中形成临时文件; 以及第二处理器，用于对临时文件执行二次编码，以便将其转换为压缩流数据，从而使临时文件和压缩流数据得以再现。可以在完成主编码之后使第二存储介质中的数据再现，从而可以高速地执行用于从第一存储介质读取的编码数据和将编码数据写入第二存储介质的处理。由于临时文件经受主编码，所以数据的版权受到保护。

9. 发明申请

US20060123420A1 Scheduling method, scheduling apparatus and multiprocessor system 有权
标题翻译：调度方法，调度设备和多处理器系统
公开(公告)号：US20060123420A1
公开(公告)日：2006-06-08
申请号：US11291073
申请日：2005-11-30
申请人： Naohiro Nishikawa
发明人： Naohiro Nishikawa
IPC分类号： G06F9/46
CPC分类号： G06F9/5066
摘要： A thread status managing unit organizes a plurality of threads into groups and manages the status of the thread groups. A ready queue queues thread groups in a ready state or a running state in the order of priority and, within the same priority level, in the FIFO order. An assignment list generating unit sequentially retrieves the thread groups from the ready queue. The assignment list appends a retrieved thread group to a thread assignment list only when all threads belonging to the retrieved thread group are assignable to the respective processors at the same time. A thread assigning unit assigns all threads belonging to the thread groups stored in the thread assignment list to the respective processors.
摘要翻译：线程状态管理单元将多个线程组织成组并管理线程组的状态。准备好的队列将处于就绪状态或运行状态的线程组以优先级顺序排队，并且在同一优先级别内以FIFO顺序排队。分配表生成单元从就绪队列顺序地检索线程组。只有当属于检索到的线程组的所有线程可以同时分配给相应的处理器时，分配列表将检索到的线程组添加到线程分配列表。线程分配单元将属于线程分配列表中存储的线程组的所有线程分配给各个处理器。

10. 发明授权

US08053811B2 Group 3-5 nitride semiconductor multilayer substrate, method for manufacturing group 3-5 nitride semiconductor free-standing subtrate, and semiconductor element 失效
标题翻译： 3-5族氮化物半导体多层基板，第3-5族氮化物半导体独立减渣剂的制造方法以及半导体元件
公开(公告)号：US08053811B2
公开(公告)日：2011-11-08
申请号：US11920563
申请日：2006-05-02
申请人： Kazumasa Hiramatsu , Hideto Miyake , Yoshihiko Tsuchida , Yoshinobu Ono , Naohiro Nishikawa
发明人： Kazumasa Hiramatsu , Hideto Miyake , Yoshihiko Tsuchida , Yoshinobu Ono , Naohiro Nishikawa
IPC分类号： H01L21/00
CPC分类号： H01L33/007 , H01L21/0237 , H01L21/0242 , H01L21/02458 , H01L21/0254 , H01L21/0262 , H01L21/02642 , H01S2304/12
摘要： A group 3-5 nitride semiconductor multilayer substrate (1) and a method for manufacturing such substrate are provided. A semiconductor layer (12) is formed on a base substrate (11), and a mask (13) is formed on the semiconductor layer (12). Then, after forming a group 3-5 nitride semiconductor crystalline layer (14) by selective growing, the group 3-5 nitride semiconductor crystalline layer (14) and the base substrate (11) are separated. The crystallinity of the semiconductor layer (12) is lower than that of the group 3-5 nitride semiconductor crystalline layer (14).
摘要翻译：提供3-5族氮化物半导体多层基板（1）及其制造方法。半导体层（12）形成在基底（11）上，在半导体层（12）上形成掩模（13）。然后，通过选择性生长形成3-5族氮化物半导体结晶层（14）后，分离3-5族氮化物半导体结晶层（14）和基底基板（11）。半导体层（12）的结晶度低于3-5族氮化物半导体晶体层（14）的结晶度。

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