专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08478215B2 Harmonic rejection mixer and phase adjustment method thereof 失效
标题翻译：谐波抑制混频器及其相位调整方法
公开(公告)号：US08478215B2
公开(公告)日：2013-07-02
申请号：US13137036
申请日：2011-07-15
申请人： Naohiro Matsui
发明人： Naohiro Matsui
IPC分类号： H03D7/16 , H04B1/10
CPC分类号： H03D7/18 , H03D7/165
摘要： A harmonic rejection mixer converts a frequency of a radio frequency signal by using a first to a third local signals (LOs) whose phases are different from each other, and the harmonic rejection mixer includes a phase difference detection circuit for detecting a phase difference between the first LO and the second LO, a phase difference detection circuit for detecting a phase difference between the first LO and the third LO, a phase adjustment circuit for adjusting the phase of the second LO so that the phase difference detected by the phase difference detection circuit becomes a first phase difference, and a phase adjustment circuit for adjusting the phase of the third LO so that the phase difference detected by the phase difference detection circuit becomes a second phase difference. It is thereby possible to achieve high precision harmonic rejection characteristics.
摘要翻译：谐波抑制混频器通过使用相位彼此不同的第一至第三本地信号（LO）来转换射频信号的频率，并且谐波抑制混频器包括相位差检测电路，用于检测相位差第一LO和第二LO，用于检测第一LO和第三LO之间的相位差的相位差检测电路，用于调整第二LO的相位的相位调整电路，使得由相位差检测电路检测的相位差成为第一相位差，以及相位调整电路，用于调整第三LO的相位，使得由相位差检测电路检测的相位差成为第二相位差。从而可以实现高精度的谐波抑制特性。

2. 发明授权

US07696789B2 High-frequency signal detector 有权
标题翻译：高频信号检测器
公开(公告)号：US07696789B2
公开(公告)日：2010-04-13
申请号：US12153815
申请日：2008-05-23
申请人： Naohiro Matsui
发明人： Naohiro Matsui
IPC分类号： H03D3/00
CPC分类号： H03D1/18 , H03F3/45085 , H03F3/45511 , H03F2200/78 , H03F2200/99
摘要： Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal. The circuit further includes a binarization circuit for receiving the output signal of the differential-input/single-ended output amplifier and comparing the output signal with a threshold voltage to thereby binarize and output the signal. The threshold voltage is adjustably set.
摘要翻译：公开了一种高频信号检测器电路，其包括用于通过二极管检测来检测输入信号的二极管检测器电路; 具有共模反馈电路的差分输入/差分输出放大器，该放大器包括用于差分地接收二极管检测器电路的输出并输出差分输出信号的差分放大电路，以及用于控制差分放大电路的共模反馈电路使得对应于来自差分放大电路的差分输出信号的中点的电压将接受与规定电压相同的电压; 以及用于接收差分放大电路的差分输出信号并输出单端输出信号的差分输入/单端输出放大器。该电路还包括用于接收差分输入/单端输出放大器的输出信号的二值化电路，并将输出信号与阈值电压进行比较，从而二值化并输出信号。阈值电压可调。

3. 发明授权

US07649418B2 Variable-gain amplifier 有权
标题翻译：可变增益放大器
公开(公告)号：US07649418B2
公开(公告)日：2010-01-19
申请号：US11760866
申请日：2007-06-11
申请人： Naohiro Matsui
发明人： Naohiro Matsui
IPC分类号： H03G3/10
CPC分类号： H03G1/0029 , H03F3/45188
摘要： There is provided a variable-gain amplifier, including two cascode amplifiers and an attenuator. The cascode amplifiers are mutually connected in parallel via the attenuator.
摘要翻译：提供了一种可变增益放大器，包括两个共源共栅放大器和一个衰减器。共源共栅放大器通过衰减器并联连接。

4. 发明申请

US20120200440A1 A/D CONVERTER AND SEMICONDUCTOR DEVICE 审中-公开
标题翻译： A / D转换器和半导体器件
公开(公告)号：US20120200440A1
公开(公告)日：2012-08-09
申请号：US13359310
申请日：2012-01-26
申请人： Hiroyuki OKADA , Naohiro MATSUI
发明人： Hiroyuki OKADA , Naohiro MATSUI
IPC分类号： H03M3/02 , H03M1/12
CPC分类号： H03M3/38 , H03M3/382 , H03M3/43 , H03M3/456
摘要： An A/D converter and a semiconductor device simple in configuration are provided which can keep a constant noise shaping characteristic without depending on manufacturing variations or a temperature change. A semiconductor device includes a delta-sigma modulator, an input changeover switch, and a control logic circuit. The delta-sigma modulator can change a time constant of an internal circuit according to a control signal. The input changeover switch selectively inputs any one of an input amplitude voltage and a reference voltage to the delta-sigma modulator. A control logic circuit is coupled to an output of the delta-sigma modulator, and generates the control signal.
摘要翻译：提供一种A / D转换器和简单构造的半导体器件，其可以保持恒定的噪声整形特性而不依赖于制造变化或温度变化。半导体器件包括Δ-Σ调制器，输入转换开关和控制逻辑电路。 Δ-Σ调制器可以根据控制信号改变内部电路的时间常数。输入切换开关选择性地将输入幅度电压和参考电压中的任何一个输入到Δ-Σ调制器。控制逻辑电路耦合到Δ-Σ调制器的输出，并产生控制信号。

5. 发明授权

US06466067B2 PLL circuit with shortened lock-up time 失效
标题翻译： PLL电路缩短锁定时间
公开(公告)号：US06466067B2
公开(公告)日：2002-10-15
申请号：US09921625
申请日：2001-08-03
申请人： Naohiro Matsui
发明人： Naohiro Matsui
IPC分类号： H03L706
CPC分类号： H03L7/095 , H03L7/10 , H03L7/107 , H03L2207/12 , Y10S331/02
摘要： BPF having a band width of |reference signal fREF-mixer output signal fMIX OUT| is connected to a phase comparator. When an output signal corresponding to the passage of this band width has been obtained, a changeover switch is turned OFF. Upon detection such that the PLL circuit is unlockable, an output signal is obtained from an offset differential pair circuit, the changeover switch is turned ON, and the time constant of LPF is reduced to shorten the lock-up time, and the voltage applied to VCO is made larger than the usual voltage. By virtue of this construction, a PLL circuit of an analog system can be realized which can shorten the lock-up time and, in addition, can reduce noise and spurious harmonics.
摘要翻译： BPF具有参考信号fREF混频器输出信号fMIX OUT |的带宽连接到相位比较器。当获得与该带宽的通过相对应的输出信号时，切换开关被切断。在检测到PLL电路可解锁时，从偏移差分对电路获得输出信号，转换开关导通，LPF的时间常数减小以缩短锁定时间，施加到 VCO被制成大于通常的电压。通过这种结构，可以实现模拟系统的PLL电路，这可以缩短锁定时间，并且还可以减少噪声和杂散谐波。

6. 发明申请

US20120064850A1 Harmonic rejection mixer and phase adjustment method thereof 失效
标题翻译：谐波抑制混频器及其相位调整方法
公开(公告)号：US20120064850A1
公开(公告)日：2012-03-15
申请号：US13137036
申请日：2011-07-15
申请人： Naohiro Matsui
发明人： Naohiro Matsui
IPC分类号： H04W4/00
CPC分类号： H03D7/18 , H03D7/165
摘要： A harmonic rejection mixer converts a frequency of a radio frequency signal by using a first to a third local signals (LOs) whose phases are different from each other, and the harmonic rejection mixer includes a phase difference detection circuit for detecting a phase difference between the first LO and the second LO, a phase difference detection circuit for detecting a phase difference between the first LO and the third LO, a phase adjustment circuit for adjusting the phase of the second LO so that the phase difference detected by the phase difference detection circuit becomes a first phase difference, and a phase adjustment circuit for adjusting the phase of the third LO so that the phase difference detected by the phase difference detection circuit becomes a second phase difference. It is thereby possible to achieve high precision harmonic rejection characteristics.
摘要翻译：谐波抑制混频器通过使用相位彼此不同的第一至第三本地信号（LO）来转换射频信号的频率，并且谐波抑制混频器包括相位差检测电路，用于检测相位差第一LO和第二LO，用于检测第一LO和第三LO之间的相位差的相位差检测电路，用于调整第二LO的相位的相位调整电路，使得由相位差检测电路检测的相位差成为第一相位差，以及相位调整电路，用于调整第三LO的相位，使得由相位差检测电路检测的相位差成为第二相位差。从而可以实现高精度的谐波抑制特性。

7. 发明申请

US20100148868A1 Differential amplifier 有权
标题翻译：差分放大器
公开(公告)号：US20100148868A1
公开(公告)日：2010-06-17
申请号：US12591933
申请日：2009-12-04
申请人： Naohiro Matsui
发明人： Naohiro Matsui
IPC分类号： H03F3/45
CPC分类号： H03F3/45188 , H03F3/195 , H03F2200/451 , H03F2203/45318 , H03F2203/45352 , H03F2203/45516 , H03F2203/45528 , H03F2203/45638 , H03F2203/45641 , H03F2203/45644 , H03F2203/45648 , H03F2203/45698 , H03F2203/45702
摘要： In a wireless communications system, it is important to realize a limiter operation by which a differential amplifier for amplifying a local signal may stably supply an output signal having a constant amplitude. However, when a signal handled by the system has a high frequency, a gain of the differential amplifier is reduced and the limiter operation may not be performed appropriately. The differential amplifier is configured employing a double cascode connection to enhance an output impedance, an upper transistor of the double cascode connection realizes enhancement in gain and frequency characteristics based on a positive feedback signal, and a lower transistor of the double cascode connection controls an operating point and suppresses an allowable output voltage range by operating in a linear region and based on a negative feedback signal to facilitate the limiter operation.
摘要翻译：在无线通信系统中，重要的是实现用于放大本地信号的差分放大器可以稳定地提供具有恒定幅度的输出信号的限幅器操作。然而，当由系统处理的信号具有高频率时，差分放大器的增益减小，并且可能不能适当地执行限幅器操作。差分放大器被配置为采用双共源共栅连接来增强输出阻抗，双共源共栅连接的上部晶体管基于正反馈信号实现增益和频率特性的增强，而双共源共栅连接的较低晶体管控制操作并且通过在线性区域中操作并且基于负反馈信号来抑制允许的输出电压范围以便于限制器操作。

8. 发明申请

US20090021282A1 High-frequency signal detector 有权
标题翻译：高频信号检测器
公开(公告)号：US20090021282A1
公开(公告)日：2009-01-22
申请号：US12153815
申请日：2008-05-23
申请人： Naohiro Matsui
发明人： Naohiro Matsui
IPC分类号： G01R23/15
CPC分类号： H03D1/18 , H03F3/45085 , H03F3/45511 , H03F2200/78 , H03F2200/99
摘要： Disclosed is a high-frequency signal detector circuit including a diode detector circuit for detecting an input signal by diode detection; a differential-input/differential output amplifier with a common mode feedback circuit, the amplifier including a differential amplifying circuit for differentially receiving outputs of the diode detector circuit and outputting a differential output signal, and a common mode feedback circuit for controlling the differential amplifying circuit in such a manner that a voltage corresponding to a mid-point of the differential output signal from the differential amplifying circuit will take on a voltage identical with a prescribed voltage; and a differential-input/single-ended output amplifier for receiving the differential output signal of the differential amplifying circuit and outputting a single-ended output signal. The circuit further includes a binarization circuit for receiving the output signal of the differential-input/single-ended output amplifier and comparing the output signal with a threshold voltage to thereby binarize and output the signal. The threshold voltage is adjustably set.
摘要翻译：公开了一种高频信号检测器电路，其包括用于通过二极管检测来检测输入信号的二极管检测器电路; 具有共模反馈电路的差分输入/差分输出放大器，该放大器包括用于差分地接收二极管检测器电路的输出并输出差分输出信号的差分放大电路，以及用于控制差分放大电路的共模反馈电路使得对应于来自差分放大电路的差分输出信号的中点的电压将接受与规定电压相同的电压; 以及用于接收差分放大电路的差分输出信号并输出单端输出信号的差分输入/单端输出放大器。该电路还包括用于接收差分输入/单端输出放大器的输出信号的二值化电路，并将输出信号与阈值电压进行比较，从而二值化并输出信号。阈值电压可调。

9. 发明申请

US20070296501A1 VARIABLE-GAIN AMPLIFIER 有权
标题翻译：可变增益放大器
公开(公告)号：US20070296501A1
公开(公告)日：2007-12-27
申请号：US11760866
申请日：2007-06-11
申请人： Naohiro MATSUI
发明人： Naohiro MATSUI
IPC分类号： H03G3/00
CPC分类号： H03G1/0029 , H03F3/45188
摘要： There is provided a variable-gain amplifier, including two cascode amplifiers and an attenuator. The cascode amplifiers are mutually connected in parallel via the attenuator.
摘要翻译：提供了一种可变增益放大器，包括两个共源共栅放大器和一个衰减器。共源共栅放大器通过衰减器并联连接。

10. 发明申请

US20060170497A1 Gain variable amplifier 有权
标题翻译：增益可变放大器
公开(公告)号：US20060170497A1
公开(公告)日：2006-08-03
申请号：US11341526
申请日：2006-01-30
申请人： Tatsuhiko Maruyama , Naohiro Matsui
发明人： Tatsuhiko Maruyama , Naohiro Matsui
IPC分类号： H03F3/45
CPC分类号： H03F3/45188 , H03F2203/45052 , H03F2203/45392 , H03F2203/45466 , H03F2203/45471 , H03G1/0029 , H03G1/0035
摘要： A gain variable amplifier according to an embodiment of the present invention includes: an amplifier circuit amplifying an input signal with a variable gain; and a gain control circuit controlling the gain of the amplifier circuit based on a gain control signal, in which the amplifier circuit includes: an amplifying element amplifying the input signal; an output element series-connected with the amplifying element and outputting a signal amplified with the amplifying element; and a bias circuit changing a potential at a node between the output element and the amplifying element based on the gain control of the gain control circuit.
摘要翻译：根据本发明实施例的增益可变放大器包括：放大器电路，放大具有可变增益的输入信号; 以及增益控制电路，其基于增益控制信号来控制所述放大器电路的增益，其中所述放大器电路包括：放大元件，放大所述输入信号; 与放大元件串联连接并输出用放大元件放大的信号的输出元件; 以及偏置电路，其基于增益控制电路的增益控制来改变输出元件和放大元件之间的节点处的电位。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式