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1. 发明申请

US20080191309A1 METHODS AND STRUCTURE FOR CHARGE DISSIPATION IN INTEGRATED CIRCUITS 失效
标题翻译：集成电路充电放电的方法与结构
公开(公告)号：US20080191309A1
公开(公告)日：2008-08-14
申请号：US12103212
申请日：2008-04-15
申请人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
发明人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
IPC分类号： H01L23/58 , H01L21/762 , G06F17/50
CPC分类号： H01L23/5226 , H01L21/743 , H01L23/5286 , H01L23/585 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
摘要翻译：在SOI衬底上集成电路中设计电荷耗散结构的方法和结构及方法。第一结构包括围绕集成电路芯片的周边的电荷耗散环以及物理和电连接到电荷消耗基座的一个或多个电荷消耗基座。 SOI衬底的硅层和体硅层通过保护环和电荷消耗基座连接。集成电路芯片的地面配电网连接到一个或多个电荷消耗基座的最上面的线段。第二种结构，用额外的电荷消耗基座元件代替电荷消除保护环。

2. 发明授权

US06121129A Method of contact structure formation 失效
标题翻译：接触结构形成方法
公开(公告)号：US06121129A
公开(公告)日：2000-09-19
申请号：US784158
申请日：1997-01-15
申请人： Nancy Anne Greco , Stephen Edward Greco , Tina Jane Wagner
发明人： Nancy Anne Greco , Stephen Edward Greco , Tina Jane Wagner
IPC分类号： H01L21/28 , H01L21/768 , H01L21/4763
CPC分类号： H01L21/768 , H01L21/76877
摘要： A method of forming a semiconductor structure having features of differing sizes, includes forming a first layer on a semiconductor substrate; patterning only a first plurality of features of a first feature size on the first layer; removing portions of the first layer, the portions corresponding to the first plurality of features, filling the first plurality of openings; forming a second layer, the second layer overlying the first layer and the filled openings; patterning a second plurality of features of a second feature size on the second layer; removing portions of the first layer and second layer, the portions corresponding to the second plurality of features, the second plurality of openings extending through the first and second layers, and filling the second plurality openings.
摘要翻译：一种形成具有不同尺寸特征的半导体结构的方法，包括在半导体衬底上形成第一层; 仅在第一层上构图第一特征尺寸的第一多个特征; 去除第一层的部分，对应于第一多个特征的部分，填充第一多个开口; 形成第二层，所述第二层覆盖所述第一层和所述填充的开口; 在第二层上构图第二特征尺寸的第二多个特征; 去除第一层和第二层的部分，对应于第二多个特征的部分，第二多个开口延伸穿过第一和第二层，并填充第二多个开口。

3. 发明授权

US5928960A Process for reducing pattern factor effects in CMP planarization 失效
标题翻译：降低CMP平面化中图案因素影响的方法
公开(公告)号：US5928960A
公开(公告)日：1999-07-27
申请号：US738506
申请日：1996-10-24
申请人： Nancy Anne Greco , Stephen Edward Greco
发明人： Nancy Anne Greco , Stephen Edward Greco
IPC分类号： H01L21/3205 , H01L21/304 , H01L21/3105 , H01L21/00
CPC分类号： H01L21/31053
摘要： According to the present invention, an improved method for planarizing the surface of a dielectric or metal layer in an integrated circuit manufacturing process is disclosed. The dielectric or metal layer to be planarized is selectively patterned and etched over different regions of the surface. The size, shape, density, and depth of the patterns are determined by the pattern factor of the integrated circuit structures underlying the layer to be planarized. Further, by using the pattern factor of the underlying structures to determine the density, size, depth and placement of the surface pattern, the overall planarization process can be improved. Other empirically determined factors, such as material strength, CMP slurry temperature, and pad pressure can also be used to further refine the CMP process. By varying the pattern over the entire surface of the layer to be planarized, the CMP material removal rate can be controlled to achieve a more planar surface.
摘要翻译：根据本发明，公开了一种用于在集成电路制造工艺中平坦化电介质或金属层的表面的改进方法。要平坦化的介电层或金属层被选择性地图案化并蚀刻在表面的不同区域上。图案的尺寸，形状，密度和深度由待平坦化层下面的集成电路结构的图案因子确定。此外，通过使用下面的结构的图案因子来确定表面图案的密度，尺寸，深度和放置，可以提高整体平坦化处理。还可以使用其他经验确定的因素，例如材料强度，CMP浆料温度和垫压力来进一步改进CMP工艺。通过改变要平坦化的层的整个表面上的图案，可以控制CMP材料去除速率以实现更平坦的表面。

4. 发明授权

US07408206B2 Method and structure for charge dissipation in integrated circuits 有权
标题翻译：集成电路中电荷耗散的方法和结构
公开(公告)号：US07408206B2
公开(公告)日：2008-08-05
申请号：US11164377
申请日：2005-11-21
申请人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
发明人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
IPC分类号： H01L29/017
CPC分类号： H01L23/5226 , H01L21/743 , H01L23/5286 , H01L23/585 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
摘要翻译：在SOI衬底上集成电路中设计电荷耗散结构的方法和结构及方法。第一结构包括围绕集成电路芯片的周边的电荷耗散环以及物理和电连接到电荷消耗基座的一个或多个电荷消耗基座。 SOI衬底的硅层和体硅层通过保护环和电荷消耗基座连接。集成电路芯片的地面配电网连接到一个或多个电荷消耗基座的最上面的线段。第二种结构，用额外的电荷消耗基座元件代替电荷消除保护环。

5. 发明授权

US07300825B2 Customizing back end of the line interconnects 失效
标题翻译：定制线路互连的后端
公开(公告)号：US07300825B2
公开(公告)日：2007-11-27
申请号：US10835953
申请日：2004-04-30
申请人： Nancy Anne Greco , Stephen Edward Greco , Erik L. Hedberg
发明人： Nancy Anne Greco , Stephen Edward Greco , Erik L. Hedberg
IPC分类号： H01L21/00
CPC分类号： H01L21/76895 , H01L24/05 , H01L2224/05624 , H01L2924/12042 , H01L2924/14 , H01L2924/01029 , H01L2924/00
摘要： Custom connections between pairs of copper wires in a last damascene wiring level are effected by creating openings in an overlying insulating layer which span a distance between portions of the two wires, then filling the openings with aluminum. The openings can be created (or completed) by a second, maskless UV laser exposure of positive photoresist which is used for patterning the insulating layer. If an opening is not created, an aluminum connecting shape overlying the insulating layer will not effect a connection between the two wires. Similar results can be achieved by laser exposure of a resist used to pattern the aluminum layer, thereby causing breaks in connecting shape when it is desired not to have a connection.
摘要翻译：在最后一个镶嵌布线层次中的铜线对之间的定制连接是通过在覆盖的绝缘层中形成开口，跨越两条线的部分之间的距离，然后用铝填充开口。可以通过用于图案化绝缘层的正性光致抗蚀剂的第二次无掩模UV激光曝光来创建（或完成）开口。如果不产生开口，则覆盖绝缘层的铝连接形状将不会影响两条电线之间的连接。通过用于图案化铝层的抗蚀剂的激光曝光可以实现类似的结果，从而当期望不连接时，导致连接形状的断裂。

6. 发明授权

US06927440B2 Metal-insulator-metal capacitor 失效
公开(公告)号：US06927440B2
公开(公告)日：2005-08-09
申请号：US10658036
申请日：2003-09-09
申请人： Nancy Anne Greco , David Louis Harame , Gary Robert Hueckel , Joseph Thomas Kocis , Dominique Nguyen Ngoc , Kenneth Jay Stein
发明人： Nancy Anne Greco , David Louis Harame , Gary Robert Hueckel , Joseph Thomas Kocis , Dominique Nguyen Ngoc , Kenneth Jay Stein
IPC分类号： H01L27/04 , H01L21/02 , H01L21/768 , H01L21/822 , H01L23/522 , H01L27/108 , H01L29/41
CPC分类号： H01L23/5223 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

7. 发明授权

US06199269B1 Manipulation of micromechanical objects 失效
标题翻译：微机械物体的操纵
公开(公告)号：US06199269B1
公开(公告)日：2001-03-13
申请号：US08956752
申请日：1997-10-23
申请人： Nancy Anne Greco , Ernest Norman Levine , Michael F. Lofaro , James Gardner Ryan
发明人： Nancy Anne Greco , Ernest Norman Levine , Michael F. Lofaro , James Gardner Ryan
IPC分类号： B23P1900
CPC分类号： G02B26/0841 , Y10T29/4979 , Y10T29/49799 , Y10T29/53
摘要： An aid to the manipulation of microfabricated micro tools in manufacturing and assembly is disclosed. A sequence of micro tools and a manipulator are connected to one another via attachment links as a combination. The attachment links are optimized to readily allow severing of individual micro tools from the combination as needed. The manipulator provides an aid for handling the combination via probe, pliers, clasping, mating or other device. This facilitates human or machine interaction with the combination of micro tools, either for subsequent processing, or for the assembly of the micro tools into a completed product.
摘要翻译：公开了在制造和组装中对微加工微型工具的操纵的帮助。一系列微型工具和操纵器通过连接作为一个组合相互连接。附件链接被优化以容易地允许根据需要从组合中分离各个微型工具。操纵器提供了通过探头，钳子，夹紧，配合或其他装置处理组合的辅助。这有助于人类或机器与微型工具的组合相互作用，用于后续处理，或者将微型工具组装成完整的产品。

8. 发明授权

US07759173B2 Methods for charge dissipation in integrated circuits 失效
标题翻译：集成电路中的电荷耗散方法
公开(公告)号：US07759173B2
公开(公告)日：2010-07-20
申请号：US12103212
申请日：2008-04-15
申请人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
发明人： Kenneth L. DeVries , Nancy Anne Greco , Joan Preston , Stephen Larry Runyon
IPC分类号： H01L21/332
CPC分类号： H01L23/5226 , H01L21/743 , H01L23/5286 , H01L23/585 , H01L23/60 , H01L2924/0002 , H01L2924/00
摘要： Methods and structures and methods of designing structures for charge dissipation in an integrated circuit on an SOI substrate. A first structure includes a charge dissipation ring around a periphery of the integrated circuit chip and one or more charge dissipation pedestals physically and electrically connected to the charge dissipation pedestals. The silicon layer and bulk silicon layer of the SOI substrate are connected by the guard ring and the charge dissipation pedestals. The ground distribution grid of the integrated circuit chip is connected to an uppermost wire segment of one or more charge dissipation pedestals. A second structure, replaces the charge dissipation guard ring with additional charge dissipation pedestal elements.
摘要翻译：在SOI衬底上集成电路中设计电荷耗散结构的方法和结构及方法。第一结构包括围绕集成电路芯片的周边的电荷耗散环以及物理和电连接到电荷消耗基座的一个或多个电荷消耗基座。 SOI衬底的硅层和体硅层通过保护环和电荷消耗基座连接。集成电路芯片的地面配电网连接到一个或多个电荷消耗基座的最上面的线段。第二种结构，用额外的电荷消耗基座元件代替电荷消除保护环。

9. 发明授权

US06098788A Casting of complex micromechanical objects 失效
标题翻译：铸造复杂的微机械物体
公开(公告)号：US06098788A
公开(公告)日：2000-08-08
申请号：US926401
申请日：1997-09-09
申请人： Nancy Anne Greco , Ernest Norman Levine , Michael F. Lofaro , James Gardner Ryan
发明人： Nancy Anne Greco , Ernest Norman Levine , Michael F. Lofaro , James Gardner Ryan
IPC分类号： B29C33/30 , B29C33/38 , B65G33/00
CPC分类号： B29C33/38 , B29C33/302 , Y10T428/24322
摘要： A seamless micromechanical object is cast by forming a multilevel mold, filling the mold, and selectively removing the mold with respect to the micromechanical object. The mold can have a first level having a first opening therein, and a second level on the first level, the second level having a second opening therein, the second opening smaller than the first opening. The object may contain a controlled void, for example a micromechanical auger with a void formed therethrough to be used as a capillary to drain off fluids when the auger is in use.
摘要翻译：通过形成多层模具，填充模具并相对于微机械物体选择性地移除模具来铸造无缝微机械物体。模具可以具有在其中具有第一开口的第一层和第一层上的第二层，第二层在其中具有第二开口，第二开口小于第一开口。该物体可以包含受控的空隙，例如具有穿过其形成的空隙的微机械螺旋钻，用作毛细管以在使用螺旋推运器时排出流体。

10. 发明授权

US5926359A Metal-insulator-metal capacitor 失效
公开(公告)号：US5926359A
公开(公告)日：1999-07-20
申请号：US626310
申请日：1996-04-01
申请人： Nancy Anne Greco , David Louis Harame , Gary Robert Hueckel , Joseph Thomas Kocis , Dominique Nguyen Ngoc , Kenneth Jay Stein
发明人： Nancy Anne Greco , David Louis Harame , Gary Robert Hueckel , Joseph Thomas Kocis , Dominique Nguyen Ngoc , Kenneth Jay Stein
IPC分类号： H01L27/04 , H01L21/02 , H01L21/768 , H01L21/822 , H01L23/522 , H01G4/06
CPC分类号： H01L23/5223 , H01L28/40 , H01L2924/0002
摘要： An interconnection wiring system incorporating two levels of interconnection wiring separated by a first dielectric, a capacitor formed by a second dielectric, a bottom electrode of the lower interconnection wiring or a via and a top electrode of the upper interconnection wiring or a separate metal layer. The invention overcomes the problem of leakage current and of substrate stray capacitance by positioning the capacitor between two levels of interconnection wiring.

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