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1. 发明授权

US07719321B2 Short pulse rejection circuit and method thereof 有权
标题翻译：短脉冲抑制电路及其方法
公开(公告)号：US07719321B2
公开(公告)日：2010-05-18
申请号：US12289855
申请日：2008-11-06
申请人： Cheon-Oh Lee , Nam-Hyun Kim , Ki-Hong Kim , Jong-Seok Kim , Jin-Ho Oh
发明人： Cheon-Oh Lee , Nam-Hyun Kim , Ki-Hong Kim , Jong-Seok Kim , Jin-Ho Oh
IPC分类号： H03K9/08
CPC分类号： H04L7/033 , H03K5/1252 , H03K5/1534 , H04L7/0083
摘要： A short pulse rejection circuit may include an edge detector, a filter circuit, a comparison circuit, and a gating circuit. The edge detector may delay an input signal to generate a delayed input signal, and detect an edge of the input signal to generate an edge detection signal. The filter circuit may perform a low pass filtering on the edge detection signal to generate a first signal. The comparison circuit may compare the first signal with a reference voltage. The gating circuit may gate the delayed input signal based on an output signal of the comparison circuit. Therefore, the short pulse rejection circuit may have a sufficient setup/hold time margin of a flip-flop, and may sample an input signal even when a state of the input signal does not change during an initial operation.
摘要翻译：短脉冲抑制电路可以包括边缘检测器，滤波器电路，比较电路和门控电路。边缘检测器可以延迟输入信号以产生延迟的输入信号，并且检测输入信号的边沿以产生边缘检测信号。滤波器电路可以对边缘检测信号执行低通滤波以产生第一信号。比较电路可以将第一信号与参考电压进行比较。门控电路可以基于比较电路的输出信号对延迟的输入信号进行门控。因此，短脉冲抑制电路可以具有触发器的足够的建立/保持时间裕度，并且即使在初始操作期间输入信号的状态没有改变时，也可以采样输入信号。

2. 发明申请

US20090072810A1 Voltage-drop measuring circuit, semiconductor device and system having the same, and associated methods 审中-公开
标题翻译：电压降测量电路，具有相同的半导体器件和系统及相关方法
公开(公告)号：US20090072810A1
公开(公告)日：2009-03-19
申请号：US12232140
申请日：2008-09-11
申请人： Cheon-Oh Lee , Nam-Hyun Kim , Dong-Chul Choi
发明人： Cheon-Oh Lee , Nam-Hyun Kim , Dong-Chul Choi
IPC分类号： G01R19/165
CPC分类号： G01R19/16552
摘要： A voltage-drop measuring circuit is capable of measuring a voltage-drop of a power supply voltage caused by a resistance component of a power line. The voltage-drop measuring circuit includes a sensing circuit and a voltage-drop detecting circuit. The sensing circuit includes a sensor configured to generate a sensing voltage received by the sensor from a power pad through a power line between the sensor and the power pad. The voltage-drop detecting circuit is arranged in a neighborhood of a power pad, and is configured to generate a reference voltage, compare the sensing voltage with the reference voltage to detect the voltage-drop, and generate a detecting signal in accordance with the voltage-drop.
摘要翻译：电压降测量电路能够测量由电力线的电阻分量引起的电源电压的电压降。电压降测量电路包括感测电路和电压降检测电路。感测电路包括传感器，其被配置为通过传感器和电源板之间的电力线从功率垫产生由传感器接收的感测电压。电压降检测电路被布置在电源焊盘的附近，并且被配置为产生参考电压，将感测电压与参考电压进行比较以检测电压降，并根据电压产生检测信号 -下降。

3. 发明申请

US20090189644A1 Short pulse rejection circuit and method thereof 有权
标题翻译：短脉冲抑制电路及其方法
公开(公告)号：US20090189644A1
公开(公告)日：2009-07-30
申请号：US12289855
申请日：2008-11-06
申请人： Cheon-Oh Lee , Nam-Hyun Kim , Ki-Hong Kim , Jong-Seok Kim , Jin-Ho Oh
发明人： Cheon-Oh Lee , Nam-Hyun Kim , Ki-Hong Kim , Jong-Seok Kim , Jin-Ho Oh
IPC分类号： G01R29/02
CPC分类号： H04L7/033 , H03K5/1252 , H03K5/1534 , H04L7/0083
摘要： A short pulse rejection circuit may include an edge detector, a filter circuit, a comparison circuit, and a gating circuit. The edge detector may delay an input signal to generate a delayed input signal, and detect an edge of the input signal to generate an edge detection signal. The filter circuit may perform a low pass filtering on the edge detection signal to generate a first signal. The comparison circuit may compare the first signal with a reference voltage. The gating circuit may gate the delayed input signal based on an output signal of the comparison circuit. Therefore, the short pulse rejection circuit may have a sufficient setup/hold time margin of a flip-flop, and may sample an input signal even when a state of the input signal does not change during an initial operation.
摘要翻译：短脉冲抑制电路可以包括边缘检测器，滤波器电路，比较电路和门控电路。边缘检测器可以延迟输入信号以产生延迟的输入信号，并且检测输入信号的边沿以产生边缘检测信号。滤波器电路可以对边缘检测信号执行低通滤波以产生第一信号。比较电路可以将第一信号与参考电压进行比较。门控电路可以基于比较电路的输出信号对延迟的输入信号进行门控。因此，短脉冲抑制电路可以具有触发器的足够的建立/保持时间裕度，并且即使当在初始操作期间输入信号的状态不改变时，也可以采样输入信号。

4. 发明申请

US20120008017A1 IMAGE SENSOR AND PIXEL CORRECTION METHOD 审中-公开
标题翻译：图像传感器和像素校正方法
公开(公告)号：US20120008017A1
公开(公告)日：2012-01-12
申请号：US12982498
申请日：2010-12-30
申请人： Yeon-U JEONG , Kwan-Youl Lee , Geon-Pyo Kim , Nam-Hyun Kim
发明人： Yeon-U JEONG , Kwan-Youl Lee , Geon-Pyo Kim , Nam-Hyun Kim
IPC分类号： H04N9/64 , H04N5/217
CPC分类号： H04N5/3675
摘要： An image sensor includes a corrector configured to receive a bayer raw data of a pixel array and output a corrected pixel value by correcting a dead pixel occurring in the pixel array, a memory configured to store the corrected pixel value updated in real-time, and a controller configured to control the real-time updating of the corrected pixel value to be stored in the memory, wherein when the corrector corrects the dead pixel in response to a clock, the corrector uses the corrected pixel value which is updated and stored in the memory in response to a previous cycle of the clock.
摘要翻译：图像传感器包括：校正器，被配置为接收像素阵列的拜耳原始数据，并且通过校正像素阵列中出现的死像素输出校正像素值;存储器，被配置为存储实时更新的校正像素值;以及控制器，被配置为控制要存储在存储器中的校正像素值的实时更新，其中当校正器响应于时钟校正死像素时，校正器使用更新并存储在存储器中的校正像素值响应于上一个时钟周期的内存。

5. 发明授权

US07796063B2 Data transmission circuits and data transceiver systems 有权
标题翻译：数据传输电路和数据收发器系统
公开(公告)号：US07796063B2
公开(公告)日：2010-09-14
申请号：US12289889
申请日：2008-11-06
申请人： Jong-Seok Kim , Nam-Hyun Kim , Cheon-Oh Lee , Han-Kyul Lim
发明人： Jong-Seok Kim , Nam-Hyun Kim , Cheon-Oh Lee , Han-Kyul Lim
IPC分类号： H03M9/00
CPC分类号： H03M9/00 , H03K5/135
摘要： A transmission circuit includes a serial clock generator, a serializer and a transmission clock generator. The serial clock generator generates a serial clock. The serializer serializes N-bit parallel data to N-bit serial data in synchronization with the serial clock. The transmission clock generator receives the serial clock to generate a transmission clock that has a same delay as the N-bit serial data, and the data transmission circuit simultaneously transmits the N-bit serial data and the serial clock.
摘要翻译：传输电路包括串行时钟发生器，串行器和传输时钟发生器。串行时钟发生器产生串行时钟。串行器与串行时钟同步将N位并行数据串行化为N位串行数据。传输时钟发生器接收串行时钟以产生与N位串行数据具有相同延迟的传输时钟，并且数据传输电路同时发送N位串行数据和串行时钟。

6. 发明申请

US20090167573A1 Data transmission circuits and data transceiver systems 有权
标题翻译：数据传输电路和数据收发器系统
公开(公告)号：US20090167573A1
公开(公告)日：2009-07-02
申请号：US12289889
申请日：2008-11-06
申请人： Jong-Seok Kim , Nam-Hyun Kim , Cheon-Oh Lee , Han-Kyul Lim
发明人： Jong-Seok Kim , Nam-Hyun Kim , Cheon-Oh Lee , Han-Kyul Lim
IPC分类号： H03M9/00 , H04B1/38
CPC分类号： H03M9/00 , H03K5/135
摘要： A data transmission circuit is disclosed. The transmission circuit includes a serial clock generator, a serializer and a transmission clock generator. The serial clock generator generates a serial clock. The serializer serializes N-bit parallel data to N-bit serial data in synchronization with the serial clock. The transmission clock generator receives the serial clock to generate a transmission clock that has a same delay as the N-bit serial data, and the data transmission circuit simultaneously transmits the N-bit serial data and the serial clock.
摘要翻译：公开了一种数据传输电路。传输电路包括串行时钟发生器，串行器和传输时钟发生器。串行时钟发生器产生串行时钟。串行器与串行时钟同步将N位并行数据串行化为N位串行数据。传输时钟发生器接收串行时钟以产生与N位串行数据具有相同延迟的传输时钟，并且数据传输电路同时发送N位串行数据和串行时钟。

7. 发明授权

US07389469B2 Bus systems, apparatuses, and methods of operating a bus 失效
标题翻译：总线系统，设备和操作总线的方法
公开(公告)号：US07389469B2
公开(公告)日：2008-06-17
申请号：US11142182
申请日：2005-06-02
申请人： Nam-Hyun Kim
发明人： Nam-Hyun Kim
IPC分类号： H03M13/00
CPC分类号： H04L25/08 , H04L1/0061 , H04L1/0072 , H04L2001/0094
摘要： Data transmission between transmitting/receiving nodes in a bus system may be controlled based on an error check of received data. When an error in the received data is detected, the transmitting node may cease data transmission, and other nodes, which may not have detected the error, may be notified of the detected error.
摘要翻译：可以基于接收到的数据的错误检查来控制总线系统中的发送/接收节点之间的数据传输。当检测到接收到的数据中的错误时，发送节点可以停止数据传输，并且可能没有检测到错误的其他节点通知检测到的错误。

8. 发明授权

US08217948B2 Display interface system, display device and display system 有权
标题翻译：显示界面系统，显示设备和显示系统
公开(公告)号：US08217948B2
公开(公告)日：2012-07-10
申请号：US12416737
申请日：2009-04-01
申请人： Dong-Chul Choi , Nam-Hyun Kim , Han-Kyul Lim
发明人： Dong-Chul Choi , Nam-Hyun Kim , Han-Kyul Lim
IPC分类号： G06T13/00
CPC分类号： G06F3/14 , G09G2370/04
摘要： A display interface system includes a display transmitter and a display receiver. The display transmitter transmits a control pattern having image type information about a type of an image to be displayed and selectively transmits image data according to the type of the image to be displayed. The display receiver receives the control pattern and selectively receives the image data based upon the image type information, reducing power consumption.
摘要翻译：显示接口系统包括显示发射机和显示接收机。显示发送器发送具有关于要显示的图像的类型的图像类型信息的控制图案，并且根据要显示的图像的类型选择性地发送图像数据。显示接收器接收控制图案，并基于图像类型信息选择性地接收图像数据，从而降低功耗。

9. 发明授权

US07223590B2 Process for preparing pravastatin sodium 失效
标题翻译：制备普伐他汀钠的方法
公开(公告)号：US07223590B2
公开(公告)日：2007-05-29
申请号：US10490937
申请日：2002-09-28
申请人： Nam-Hee Choi , Kon-Tae Tak , Ki-Woo Lee , Nam-Hyun Kim , Jong-Chang Jun , Yoon-Jeong Kong , Kyung-Mi Lee
发明人： Nam-Hee Choi , Kon-Tae Tak , Ki-Woo Lee , Nam-Hyun Kim , Jong-Chang Jun , Yoon-Jeong Kong , Kyung-Mi Lee
IPC分类号： C12N1/20
CPC分类号： C12R1/465 , C12P7/62 , C12P17/06
摘要： The present invention relates to a process for preparing pravastatin sodium. More specifically, in the process for preparing pravastatin sodium by adding a precursor of the pravastatin to a microorganism-culturing medium to obtain pravastatin sodium, the precursor of the pravastatin is added to a culture medium that is culturing Streptomyces carbophilus KBT229 (KCCM-10317), which is obtained by UV-mutating a Streptomyces carbophilus FERM BP-1145, and cultured to obtain the pravastatin sodium with high density and high efficiency.
摘要翻译：本发明涉及制备普伐他汀钠的方法。更具体地说，在通过向微生物培养基中添加普伐他汀的前体而获得普伐他汀钠制备普伐他汀钠的方法中，将普伐他汀的前体加入到培养链霉菌KBT229（KCCM-10317）的培养基中，通过UV链霉菌FERM BP-1145的扩增获得，培养，得到高密度，高效率的普伐他汀钠。

10. 发明申请

US20090251479A1 Display Interface System, Display Device and Display System 有权
标题翻译：显示接口系统，显示设备和显示系统
公开(公告)号：US20090251479A1
公开(公告)日：2009-10-08
申请号：US12416737
申请日：2009-04-01
申请人： Dong-Chul Choi , Nam-Hyun Kim , Han-Kyul Lim
发明人： Dong-Chul Choi , Nam-Hyun Kim , Han-Kyul Lim
IPC分类号： G09G5/00 , G06F3/038 , G09G5/36
CPC分类号： G06F3/14 , G09G2370/04
摘要： A display interface system includes a display transmitter and a display receiver. The display transmitter transmits a control pattern having image type information about a type of an image to be displayed and selectively transmits image data according to the type of the image to be displayed. The display receiver receives the control pattern and selectively receives the image data based upon the image type information, reducing power consumption.
摘要翻译：显示接口系统包括显示发射机和显示接收机。显示发送器发送具有关于要显示的图像的类型的图像类型信息的控制图案，并且根据要显示的图像的类型选择性地发送图像数据。显示接收器接收控制图案，并基于图像类型信息选择性地接收图像数据，从而降低功耗。

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