专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07190185B2 Methodology to measure many more transistors on the same test area 有权
标题翻译：在同一测试区域测量更多晶体管的方法
公开(公告)号：US07190185B2
公开(公告)日：2007-03-13
申请号：US10696320
申请日：2003-10-29
申请人： Franklin Duan , Minxuan Liu , John Walker , Nabil Monsour , Carl Monzel
发明人： Franklin Duan , Minxuan Liu , John Walker , Nabil Monsour , Carl Monzel
IPC分类号： G01R31/02
CPC分类号： G01R31/2884
摘要： A test methodology which provides that test structures, such as transistors, are arranged in a plurality of rows. A logic circuit controls which row is to be measured. An incrementer receives a triggering signal and functions as an address adder. Each time the triggering signal rises from 0 to 1, the output of the incrementer increases by 1. The output of the incrementer serves as the address input into a decoder. The decoder is connected to the rows of test structures. Preferably, each test structure contains a control circuit which is controlled by this signal (i.e., the output of the decoder). If the test structures are transistors, bias to each of the transistors can be applied separately with a common gate, source and well, and measurement can be done with a separate drain node.
摘要翻译：提供诸如晶体管的测试结构的测试方法被布置成多行。逻辑电路控制要测量哪一行。增量器接收触发信号并用作地址加法器。每当触发信号从0上升到1时，增量器的输出增加1.加法器的输出作为输入到解码器的地址。解码器连接到测试结构的行。优选地，每个测试结构包含由该信号（即解码器的输出）控制的控制电路。如果测试结构是晶体管，则可以使用公共栅极，源极和阱单独施加对每个晶体管的偏置，并且可以使用单独的漏极节点进行测量。

IPRDB

热门服务

关于我们

友情链接

联系方式