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1. 发明申请

US20090182442A1 FRAMEWORK FOR RESULTS INTERPRETATION AND GUIDED REFINEMENT OF SPECIFICATIONS FOR PLC LOGIC VERIFICATION 审中-公开
标题翻译：结果解释和指导对PLC逻辑验证规范的修订框架
公开(公告)号：US20090182442A1
公开(公告)日：2009-07-16
申请号：US12352988
申请日：2009-01-13
申请人： NAGARAJAN SETHURAMAN , Soumen De , Chengyin Yuan , Narahari K. Hunsur
发明人： NAGARAJAN SETHURAMAN , Soumen De , Chengyin Yuan , Narahari K. Hunsur
IPC分类号： G05B19/42 , G06F17/10
CPC分类号： G05B19/058 , G05B2219/13151 , G05B2219/13188
摘要： A system and method for interpreting formal verification results of PLC logic code used to control a manufacturing process, or other automated process, where the interpretation process does not require highly skilled technicians having significant experience in computer and mathematical algorithms. The verification process includes providing a verification results summary to check the compliance of the code with respect to the specifications. The verification results summary is analyzed and categorized to determine whether violations or errors are found in the results. The results can be depicted by assertion trees if a direct assertion between the PLC logic and the specifications can be provided. Alternatively, the results can be depicted by a reduced ladder logic if a direct assertion between the PLC logic and the specifications cannot be provided and a simulation is required. The specification refinement suggestions will be provided if the critical variable for violations is identified.
摘要翻译：用于解释用于控制制造过程或其他自动化过程的PLC逻辑代码的形式验证结果的系统和方法，其中解释过程不需要具有在计算机和数学算法方面具有丰富经验的高技能技术人员。验证过程包括提供验证结果摘要，以检查代码是否符合规范。对验证结果摘要进行分析和分类，以确定结果中是否发现违规或错误。如果可以提供PLC逻辑和规范之间的直接断言，则可以通过断言树来描述结果。或者，如果不能提供PLC逻辑和规范之间的直接断言并需要仿真，则结果可以通过减少的梯形逻辑来描述。如果确定违规的关键变量，将提供规范细化建议。

2. 发明申请

US20110125302A1 METHOD AND SYSTEM FOR FORMAL SAFETY VERIFICATION OF MANUFACTURING AUTOMATION SYSTEMS 审中-公开
标题翻译：制造自动化系统的正式安全验证方法与系统
公开(公告)号：US20110125302A1
公开(公告)日：2011-05-26
申请号：US12604449
申请日：2009-10-23
申请人： Nagarajan Sethuraman , Jerome O. Schroeder , Soumen De , Chengyin Yuan , Stephan R. Biller , Frank Gajor , Jeffrey J. Byrnes , Narahari K. Hunsur
发明人： Nagarajan Sethuraman , Jerome O. Schroeder , Soumen De , Chengyin Yuan , Stephan R. Biller , Frank Gajor , Jeffrey J. Byrnes , Narahari K. Hunsur
IPC分类号： G06F19/00 , G06F11/36 , G05B9/02
CPC分类号： G05B9/02 , G06F11/3604
摘要： A method and system is provided for verifying and certifying the safety logic of a manufacturing automation system including safety logic, where the logic may include one or more safety modules, routines, programs and tasks or a combination thereof; testing specifications corresponding to the safety logic; one or more formal model generators adapted for automatically transforming the safety logic and testing specifications through a logic parser into their respective mathematical models, formatted for example, as a Petri-net or binary decision diagram; a safety logic verifier configured for automatically comparing the safety logic formal model against the testing specification formal model to verify the safety logic model for the purpose of certifying the safety logic. The testing specifications may include testing of safety logic behavior including reaching safe state, remaining in safe state without reset, recovering from safe state with reset and remaining active with false alarm detection.
摘要翻译：提供了一种用于验证和认证包括安全逻辑的制造自动化系统的安全逻辑的方法和系统，其中逻辑可以包括一个或多个安全模块，例程，程序和任务或其组合; 测试规范对应于安全逻辑; 适用于通过逻辑解析器将安全逻辑和测试规范自动转换成其各自的数学模型的一个或多个形式模型发生器，其格式化为例如Petri网或二进制决策图; 安全逻辑验证器被配置用于自动地将安全逻辑形式模型与测试规范形式模型进行比较，以验证安全逻辑模型以证明安全逻辑。测试规范可能包括测试安全逻辑行为，包括达到安全状态，保持安全状态，无需重置，从安全状态恢复，并通过虚假警报检测保持活动状态。

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