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    • 2. 发明授权
    • Virtual machine hardware for RISC and CISC processors
    • 用于RISC和CISC处理器的虚拟机硬件
    • US08769508B2
    • 2014-07-01
    • US11171681
    • 2005-06-29
    • Mukesh K. Patel
    • Mukesh K. Patel
    • G06F9/45
    • G06F9/30174G06F9/30101
    • A hardware Java™ accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java™ bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt. A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java™ bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.
    • 硬件Java™加速器由解码级和微码级组成。 分解为解码和微码级允许解码级实现指令级并行性,而微码级允许将单个Java TM字节码转换为多个本地指令。 提供重发缓冲器,其存储转换的指令,并且当系统从中断返回时重新发行它们。 以这种方式,硬件加速器不必在中断时被刷新。 还使用本机PC显示器。 当本机PC在特定范围内时,硬件加速器能够将Java™字节码转换为本地指令。 当本地PC超出该范围时,硬件加速器被禁用,并且CPU对从存储器获得的本地指令进行操作。
    • 4. 发明授权
    • Java hardware accelerator using microcode engine
    • Java硬件加速器使用微码引擎
    • US08473718B2
    • 2013-06-25
    • US11538362
    • 2006-10-03
    • Mukesh K. Patel
    • Mukesh K. Patel
    • G06F9/30G06F9/40G06F15/00
    • G06F9/30174G06F9/3879
    • A hardware Java accelerator is comprised of a decode stage and a microcode stage. Separating into the decode and microcode stage allows the decode stage to implement instruction level parallelism while the microcode stage allows the conversion of a single Java bytecode into multiple native instructions. A reissue buffer is provided which stores the converted instructions and reissues them when the system returns from an interrupt. In this manner, the hardware accelerator need not be flushed upon an interrupt. A native PC monitor is also used. While the native PC is within a specific range, the hardware accelerator is enabled to convert the Java bytecodes into native instructions. When the native PC is outside the range, the hardware accelerator is disabled and the CPU operates on native instructions obtained from the memory.
    • 硬件Java加速器由解码级和微码级组成。 分解为解码和微码级允许解码级实现指令级并行性,而微代码级允许将单个Java字节码转换为多个本机指令。 提供重发缓冲器,其存储转换的指令,并且当系统从中断返回时重新发行它们。 以这种方式,硬件加速器不必在中断时被刷新。 还使用本机PC显示器。 当本机PC在特定范围内时,硬件加速器能够将Java字节码转换为本地指令。 当本地PC超出该范围时,硬件加速器被禁用,并且CPU对从存储器获得的本地指令进行操作。