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1. 发明专利

JPH07220475A DATA BUS STRUCTURE FOR ACCELERATION OF COLUMN ACCESS IN RANDOM ACCESS MEMORY 失效
公开(公告)号：JPH07220475A
公开(公告)日：1995-08-18
申请号：JP30672794
申请日：1994-12-09
申请人： MOSAID TECHNOLOGIES INC , MOSAID TECHNOLOGIES INC
发明人： GURAHAMU ARAN , FURANSOWA RAROSHIERU
IPC分类号： G11C11/407 , G11C7/10 , G11C11/409
摘要： PURPOSE: To obtain a semiconductor random access memory capable of inputting a new random column address in each clock period by accessing to a column address by fast burst rate without receiving the restriction of '2N rule'. CONSTITUTION: A read/write method for the semiconductor random access memory provided with a detecting amplifier connected to a bit line and a data bus read/write amplifier is provided with a pair of data buses which the detecting amplifier and the data bus read/write amplifier accesses to. In a first read/write cycle, one data bus is precharged and the other data bus is read or written, and in a second rad/write cycle following the first read/write cycle, the other data bus is precharged and data in the one data base is read/written at the same time.

2. 发明专利

JP2013200889A Hybrid solid-state memory system having volatile memory and non-volatile memory 审中-公开
标题翻译：具有易失性存储器和非易失性存储器的混合固态存储器系统
公开(公告)号：JP2013200889A
公开(公告)日：2013-10-03
申请号：JP2013119104
申请日：2013-06-05
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI
IPC分类号： G06F12/00
CPC分类号： G11C14/0018 , G11C11/005
摘要： PROBLEM TO BE SOLVED: To provide a hybrid solid-state memory system for storing data.SOLUTION: The solid-state memory system comprises a volatile solid-state memory, a non-volatile solid-state memory, and a memory controller. Further, a method is provided for storing data in the solid-state memory system. The method comprises the following steps. A write command is received by the memory controller. Write data is stored in the volatile memory in response to the write command. The data is transferred from the volatile memory to the non-volatile memory in response to a data transfer request.
摘要翻译：要解决的问题：提供一种用于存储数据的混合固态存储器系统。解决方案：固态存储器系统包括易失性固态存储器，非易失性固态存储器和存储器控制器。此外，提供了一种用于将数据存储在固态存储器系统中的方法。该方法包括以下步骤。存储器控制器接收写命令。响应于写命令，写数据存储在易失性存储器中。响应于数据传输请求，数据从易失性存储器传送到非易失性存储器。

3. 发明专利

JP2013077375A Non-volatile semiconductor memory having multiple external power supply parts 审中-公开
标题翻译：具有多个外部电源部件的非易失性半导体存储器
公开(公告)号：JP2013077375A
公开(公告)日：2013-04-25
申请号：JP2013016683
申请日：2013-01-31
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI , GILLINGHAM PETER
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/30 , G11C5/14 , G11C5/143 , G11C5/145 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/26
摘要： PROBLEM TO BE SOLVED: To solve a problem that converting low or lower voltage input to higher voltage to enable memory operations reduces converter efficiency, and increases size and complexity of a charge pump circuit.SOLUTION: A memory device comprises a core memory such as a flash memory for storing data. The memory device comprises a first power input part for receiving first voltage used to supply power to the flash memory. Additionally, the memory device comprises a second power input part for receiving second voltage. The memory device comprises a power management circuit configured to receive the second voltage and draw one or more internal voltage. The power management circuit supplies or conveys the internal voltage to the flash memory. The various internal voltage generated by the power management circuit (e.g., a voltage converter circuit) and supplied to the core memory enable operations such as read, program, and erase with respect to cells in the core memory.
摘要翻译：要解决的问题：为了解决将低电压或低电压输入转换为较高电压以使得存储器操作降低转换器效率并增加电荷泵电路的尺寸和复杂性的问题。解决方案：存储器件包括诸如用于存储数据的闪存的核存储器。存储器件包括用于接收用于向闪存供电的第一电压的第一电源输入部分。另外，存储器件包括用于接收第二电压的第二电源输入部分。存储器件包括被配置为接收第二电压并且抽取一个或多个内部电压的功率管理电路。电源管理电路将内部电压提供或传送到闪存。电源管理电路（例如，电压转换器电路）产生并提供给核心存储器的各种内部电压相对于核心存储器中的单元启用诸如读取，编程和擦除的操作。版权所有（C）2013，JPO＆INPIT

4. 发明专利

JP2013037712A Daisy chain arrangement of nonvolatile memory 有权
标题翻译：非易失性存储器的DAISY链条布置
公开(公告)号：JP2013037712A
公开(公告)日：2013-02-21
申请号：JP2012210614
申请日：2012-09-25
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： KIM JIN-KI
IPC分类号： G06F13/16 , G06F12/00 , G06F12/06
CPC分类号： G06F13/4247 , G06F13/1684 , G06F13/4234 , G11C16/06 , H01L24/48 , H01L2224/32145 , H01L2224/48091 , H01L2224/48145 , H01L2224/48227 , H01L2924/00014 , H01L2924/10253 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： PROBLEM TO BE SOLVED: To provide a memory system that overcomes some of the disadvantages associated with embedded flash memories and other devices.SOLUTION: A flash memory system is implemented in a system-in-package (SIP) enclosure 310, the system comprising a flash memory controller 320 and a plurality of flash memory devices 330a-330n. An SIP applied to a single package or module comprises a number of integrated circuits (chips). The flash memory controller is configured to interface with an external system and a plurality of memory devices within the SIP. The memory devices are configured in daisy chain cascade connection, controlled by the flash memory controller through commands transmitted through the daisy chain cascade.
摘要翻译：要解决的问题：提供克服与嵌入式闪存和其他设备相关的一些缺点的存储器系统。解决方案：闪存系统在系统级封装（SIP）机箱310中实现，该系统包括闪速存储器控制器320和多个闪存器件330a-330n。应用于单个封装或模块的SIP包括多个集成电路（芯片）。闪速存储器控制器被配置为与SIP内的外部系统和多个存储器设备接口。存储器设备配置为菊花链级联，由闪存控制器通过菊花链级联传输的命令控制。版权所有（C）2013，JPO＆INPIT

5. 发明专利

JP2013008386A Serial-connection memory system by output delay adjustment 有权
标题翻译：串行连接存储器系统通过输出延迟调整
公开(公告)号：JP2013008386A
公开(公告)日：2013-01-10
申请号：JP2012193816
申请日：2012-09-04
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： OH HAK JUNE
IPC分类号： G06F12/00 , G06F13/16
CPC分类号： G11C7/22 , G11C7/1066 , G11C7/1069 , G11C7/222 , G11C16/32
摘要： PROBLEM TO BE SOLVED: To provide a system and a method for performing output delay adjustment by correcting a clock duty cycle, for a serial-connection device which operates as a slave device.SOLUTION: A master device supplies a clock to a first slave device. Each slave device sends the clock to a next slave one after another. A slave device of the lowest order feeds the clock back to the master device. The master device compares the sent-out clock with the feedback clock to determine whether duty cycle correction or output delay adjustment is necessary. When the duty cycle correction or output delay adjustment is necessary, the master device generates and outputs a command to the slave device to perform the duty cycle correction or output delay adjustment. The slave devices each have a circuit which performs the duty cycle correction or output delay adjustment. In this embodiment, the respective slave devices are memory devices and the master device is a memory controller.
摘要翻译：要解决的问题：提供一种用于通过校正时钟占空比来执行输出延迟调整的系统和方法，对于作为从设备操作的串行连接设备。解决方案：主设备向第一个从设备提供时钟。每个从设备一个接一个地将时钟发送到下一个从站。最低级的从设备将时钟送回主设备。主设备将发送时钟与反馈时钟进行比较，以确定是否需要占空比校正或输出延迟调整。当需要占空比校正或输出延迟调整时，主器件产生并向从器件输出命令以执行占空比校正或输出延迟调整。从设备各自具有执行占空比校正或输出延迟调整的电路。在本实施例中，各个从设备是存储设备，主设备是存储器控制器。版权所有（C）2013，JPO＆INPIT

6. 发明专利

JP2012100275A Method and apparatus for adaptive data compression 审中-公开
标题翻译：自适应数据压缩的方法和装置
公开(公告)号：JP2012100275A
公开(公告)日：2012-05-24
申请号：JP2011252669
申请日：2011-11-18
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： MOURAD ABDAT
IPC分类号： H03M7/40 , H03M7/42 , H03M7/30
CPC分类号： H03M7/3088
摘要： PROBLEM TO BE SOLVED: To provide a method and apparatus for performing adaptive data compression.SOLUTION: Each time an unknown symbol is to be encoded by an encoder, the encoder adds the symbol to a dictionary and transmits it in plain in an encoded string. The state of a prefix bit preceding a code word indicates whether the code word is a plain symbol or an index of a symbol or string of symbols stored in the dictionary. If the code word stores a symbol in plain, a decoder learns the symbol by adding a sequence of symbols resulting from the concatenation of previously decoded symbols and the first symbol of the currently decoded symbol and by adding the symbol to its dictionary. If the code word stores an index, the decoder decodes the code word by extracting the symbol or sequence of symbols stored in the dictionary at the respective index in the dictionary.
摘要翻译：要解决的问题：提供一种用于执行自适应数据压缩的方法和装置。解决方案：每当编码器对未知符号进行编码时，编码器将符号添加到字典中，并以编码字符串的形式传输。代码字之前的前缀位的状态指示代码字是否是存储在字典中的符号或符号串的索引。如果代码字平原存储符号，则解码器通过将从先前解码的符号和当前解码的符号的第一符号的级联产生的符号序列相加并通过将符号添加到其字典来学习该符号。如果码字存储索引，则解码器通过在字典中的相应索引处提取存储在字典中的符号或符号序列来解码码字。版权所有（C）2012，JPO＆INPIT

7. 发明专利

JP2011222117A Semiconductor memory asynchronous pipeline 有权
标题翻译：半导体存储器异步管道
公开(公告)号：JP2011222117A
公开(公告)日：2011-11-04
申请号：JP2011147610
申请日：2011-07-01
申请人： Mosaid Technologies Inc , モーセッド・テクノロジーズ・インコーポレイテッドMosaid Technologies 1ncorporated
发明人： MES IAN
IPC分类号： G11C11/407 , G11C7/10
CPC分类号： G11C7/106 , G11C7/1039 , G11C7/1051
摘要： PROBLEM TO BE SOLVED: To provide an asynchronous pipeline type semiconductor memory.SOLUTION: An SDRAM that is asynchronously pipelined includes separate pipeline stages which are controlled by asynchronous signals. Rather than using a clock signal to synchronize data in each stage, an asynchronous signal 28 is used to latch data in all stages. An asynchronous control signal is generated in a chip, and optimized to different waiting time stages 27. The data is synchronized to a clock at an end of a reading data path 24 before being read from the chip. Since the data is latched in each pipeline stage, a skew occurring in the data is smaller than ones found in a conventional wave pipeline architecture. In addition, since there is no relationship between the stages and a system clock CLK, the reading data path can be processed in any CAS waiting time only by forming a resynchronization output so as to support the reading data path.
摘要翻译：要解决的问题：提供异步流水线式半导体存储器。解决方案：异步流水线的SDRAM包括由异步信号控制的单独的流水线级。不是使用时钟信号来同步每个级中的数据，而是使用异步信号28来锁存所有级的数据。在芯片中产生异步控制信号，并且被优化到不同的等待时间段27.在从芯片读取之前，将数据同步到读取数据路径24的末端处的时钟。由于数据在每个流水线阶段被锁存，所以在数据中发生的偏斜小于常规波形管线架构中发现的偏斜。此外，由于级与系统时钟CLK之间没有关系，所以只要通过形成再同步输出来支持读取数据路径，则可以在任何CAS等待时间内处理读取数据路径。版权所有（C）2012，JPO＆INPIT

8. 发明专利

JP2011182467A High output impedance charge pump for pll/dll 有权
标题翻译： PLL / DLL的高输出阻抗充电泵
公开(公告)号：JP2011182467A
公开(公告)日：2011-09-15
申请号：JP2011128367
申请日：2011-06-08
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： HAERLE DIETER
IPC分类号： H03L7/093 , H02M3/07 , H03L7/00 , H03L7/06 , H03L7/08 , H03L7/081 , H03L7/089
CPC分类号： H03L7/0895 , H03L7/0812
摘要： PROBLEM TO BE SOLVED: To minimize the static phase error in a charge pump. SOLUTION: A charge pump for use in a phase locked loop/delay locked loop includes a pull-up circuit, a pull-down circuit and an operational amplifier. The charge pump is designed to minimize the static phase error associated with the operation of the pull-up and pull-down circuits. The use of the operational amplifier also mitigate the effects of low power supply voltage. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：最小化电荷泵中的静态相位误差。解决方案：用于锁相环/延迟锁定环的电荷泵包括上拉电路，下拉电路和运算放大器。电荷泵被设计为最小化与上拉和下拉电路的操作相关的静态相位误差。使用运算放大器还可以减轻低电源电压的影响。版权所有（C）2011，JPO＆INPIT

9. 发明专利

JP2011091998A Adapter for mounting faceplate of first style on to electrical outlet cavity of second style 有权
标题翻译：用于安装第一种风格的适配器到第二种风格的电气出口空间
公开(公告)号：JP2011091998A
公开(公告)日：2011-05-06
申请号：JP2010272382
申请日：2010-12-07
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： BINDER YEHUDA , HAZANI AMI
IPC分类号： H02G3/02
摘要： PROBLEM TO BE SOLVED: To provide an adapter for mounting electrical outlet faceplates designed for mounting on rectangular junction boxes in hollow walls onto solid walls with cylindrical cavities and sleeves. SOLUTION: Junction box mounting is popular in North America, whereas cavity mounting is popular in Europe and the Middle East. Such an adapter provides universal mounting for specialized faceplates which are designed and intended for junction box mounting. The adapter features clamps for gripping the inner surface of a wall cavity or sleeve and a rectangular plate for mounting a faceplate designed for junction box mounting. The rectangular plate has mounting points with a nominal center-to-center distance of 31/4 inches, corresponding to the requirements of junction box mounting. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供用于安装电气出口面板的适配器，其设计用于将中空壁上的矩形接线盒安装到具有圆柱形腔和套筒的实心壁上。
解决方案：接线盒安装在北美非常受欢迎，而腔体安装在欧洲和中东受欢迎。这种适配器为专门用于接线盒安装的专门面板提供通用安装。适配器具有用于夹紧壁腔或套筒内表面的夹具和用于安装用于接线盒安装的面板的矩形板。矩形板具有安装点，其标称中心到中心距离为31/4英寸，对应于接线盒安装的要求。版权所有（C）2011，JPO＆INPIT

10. 发明专利

JP2011023366A Outlet add-on module 审中-公开
标题翻译： OUTLET ADD-ON模块
公开(公告)号：JP2011023366A
公开(公告)日：2011-02-03
申请号：JP2010215269
申请日：2010-09-27
申请人： Mosaid Technologies Inc , モサイド・テクノロジーズ・インコーポレーテッド
发明人： BINDER YEHUDA , HAZANI AMI , KOBI RAFAEL GIL , BUTBUL SHLOMO
IPC分类号： H01R31/06 , H01R13/719 , H04B3/54 , H04B3/56
CPC分类号： H04B3/542 , H01R13/719 , H01R31/065 , H04B2203/5408
摘要： PROBLEM TO BE SOLVED: To provide a method and a system to realize a high performance of an outlet easily and simply without requiring an installation by an expert. SOLUTION: This relates to a method and a device to achieve a high performance of an existing outlet by adding a function to the existing service outlet in a building (for example, LAN, telephone, power, or CATV outlet). This function is added by an add-on module (30) which is electrically connected to the existing outlet (42) and mechanically fixed. Several installation devices are illustrated including a surface mounting, side clamping, snap locking, fixing by a string, and screwing. The add-on module may include a service connector (263) which maintains a basic function of the existing outlet. The module is installed permanently or detachably. COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供一种容易且简单地实现出口的高性能的方法和系统，而不需要专家的安装。解决方案：这涉及通过向建筑物中的现有服务插座（例如LAN，电话，电源或CATV插座）增加功能来实现现有插座的高性能的方法和设备。该功能通过电连接到现有出口（42）并机械固定的附加模块（30）来添加。示出了几个安装设备，包括表面安装，侧面夹紧，卡扣锁定，通过弦线固定和旋拧。附加模块可以包括保持现有插座的基本功能的服务连接器（263）。该模块永久或可拆卸地安装。版权所有（C）2011，JPO＆INPIT

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