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1. 发明申请

US20090001601A1 MEMORY ARRAY ON MORE THAN ONE DIE 有权
标题翻译：内存阵列超过一颗
公开(公告)号：US20090001601A1
公开(公告)日：2009-01-01
申请号：US11771054
申请日：2007-06-29
申请人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Jeffrey P. Rupley, II , Edward A. Brekelbaum , Gabriel H. Loh , Bryan Black
发明人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Jeffrey P. Rupley, II , Edward A. Brekelbaum , Gabriel H. Loh , Bryan Black
IPC分类号： H01L23/48
CPC分类号： G11C7/18 , G11C5/025 , G11C7/1048 , H01L25/0655 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。还公开了其他实施例。

2. 发明授权

US08059441B2 Memory array on more than one die 有权
标题翻译：内存阵列在多个模具上
公开(公告)号：US08059441B2
公开(公告)日：2011-11-15
申请号：US12709620
申请日：2010-02-22
申请人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
发明人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C5/025 , G11C7/1048 , H01L25/0655 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。还公开了其他实施例。

3. 发明申请

US20140010000A1 APPARATUS AND METHOD FOR IMPROVING POWER DELIVERY IN A MEMORY, SUCH AS, A RANDOM ACCESS MEMORY 有权
标题翻译：用于改善存储器中的功率传输的装置和方法，例如随机访问存储器
公开(公告)号：US20140010000A1
公开(公告)日：2014-01-09
申请号：US13976858
申请日：2011-12-28
申请人： Mohammed H. Taufique , Daniel J. Cummings , Hieu T. Ngo , Shantanu Ganguly
发明人： Mohammed H. Taufique , Daniel J. Cummings , Hieu T. Ngo , Shantanu Ganguly
IPC分类号： G11C11/4091
CPC分类号： G11C11/4091 , G11C7/12 , G11C11/417
摘要： Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform a first phase of a pre-charge of a bit line and a second voltage supply rail configured to provide a second voltage amount to perform a second phase of the pre-charge of the bit line are described herein. In embodiments, the pre-charge circuit may be a pre charge circuit for a static random-access memory (SRAM) memory cell.
摘要翻译：一种用于改善功率传递的装置和方法的实施例，包括预充电电路，该预充电电路可以包括被配置为提供第一电压量以执行位线的预充电的第一相位的第一电压供应导轨和第二电压源这里描述了被配置为提供第二电压量以执行位线的预充电的第二相位的导轨。在实施例中，预充电电路可以是用于静态随机存取存储器（SRAM）存储器单元的预充电电路。

4. 发明授权

US06240024B1 Method and apparatus for generating an echo clock in a memory 有权
标题翻译：用于在存储器中产生回波时钟的方法和装置
公开(公告)号：US06240024B1
公开(公告)日：2001-05-29
申请号：US09546022
申请日：2000-04-10
申请人： Mohammed H. Taufique , Dong-Sun Min , Hemanshu T. Vernenker
发明人： Mohammed H. Taufique , Dong-Sun Min , Hemanshu T. Vernenker
IPC分类号： G11C700
CPC分类号： G11C7/06 , G11C11/4076 , G11C11/4094
摘要： A method and apparatus for generating an echo clock is described. An echo clock is an output strobe signal that selectively follows an input clock signal in a synchronous memory system and indicates when valid output data is available. The same clock signals used to change the state of an echo clock are used to output data from a memory buffer. The data buffer and echo clock buffer/generator are substantially identical in construction and operation, thereby ensuring a close correlation between a change in state of the echo clock and the availability of valid data. Such a memory provides matching of the echo clock transitions with that of the data signals on the data lines of the memory for any frequency range.
摘要翻译：描述了一种用于产生回波时钟的方法和装置。回波时钟是选择性地跟随同步存储器系统中的输入时钟信号的输出选通信号，并且指示何时有效的输出数据可用。用于改变回波时钟状态的相同时钟信号用于从存储器缓冲器输出数据。数据缓冲器和回波时钟缓冲器/发生器在结构和操作上基本相同，从而确保回波时钟的状态改变与有效数据的可用性之间的密切相关。这样的存储器提供了对于任何频率范围，回波时钟转换与存储器的数据线上的数据信号的匹配。

5. 发明授权

US08934314B2 Apparatus and method for improving power delivery in a memory, such as, a random access memory 有权
标题翻译：用于改善诸如随机存取存储器的存储器中的功率传递的装置和方法
公开(公告)号：US08934314B2
公开(公告)日：2015-01-13
申请号：US13976858
申请日：2011-12-28
申请人： Mohammed H. Taufique , Daniel J. Cummings , Hieu T. Ngo , Shantanu Ganguly
发明人： Mohammed H. Taufique , Daniel J. Cummings , Hieu T. Ngo , Shantanu Ganguly
IPC分类号： G11C7/00 , G11C11/4091 , G11C7/12 , G11C11/417
CPC分类号： G11C11/4091 , G11C7/12 , G11C11/417
摘要： Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform a first phase of a pre-charge of a bit line and a second voltage supply rail configured to provide a second voltage amount to perform a second phase of the pre-charge of the bit line are described herein. In embodiments, the pre-charge circuit may be a pre charge circuit for a static random-access memory (SRAM) memory cell.
摘要翻译：一种用于改善功率传递的装置和方法的实施例，包括预充电电路，该预充电电路可以包括被配置为提供第一电压量以执行位线的预充电的第一相位的第一电压供应导轨和第二电压源这里描述了被配置为提供第二电压量以执行位线的预充电的第二相位的导轨。在实施例中，预充电电路可以是用于静态随机存取存储器（SRAM）存储器单元的预充电电路。

6. 发明授权

US07692946B2 Memory array on more than one die 有权
标题翻译：内存阵列在多个模具上
公开(公告)号：US07692946B2
公开(公告)日：2010-04-06
申请号：US11771054
申请日：2007-06-29
申请人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
发明人： Mohammed H. Taufique , Derwin Jallice , Donald W. McCauley , John P. DeVale , Edward A. Brekelbaum , Jeffrey P. Rupley, II , Gabriel H. Loh , Bryan Black
IPC分类号： G11C5/06
CPC分类号： G11C7/18 , G11C5/025 , G11C7/1048 , H01L25/0655 , H01L25/0657 , H01L2924/0002 , H01L2924/00
摘要： For one disclosed embodiment, an apparatus may comprise a first die including a first plurality of memory cells for a memory array and a second die including a second plurality of memory cells for the memory array. The second die may include a shared line for the memory array to conduct digital signals for memory cells of both the first and second plurality of memory cells. Other embodiments are also disclosed.
摘要翻译：对于一个公开的实施例，装置可以包括第一管芯，其包括用于存储器阵列的第一多个存储单元和包括用于存储器阵列的第二多个存储单元的第二管芯。第二管芯可以包括用于存储器阵列的共享线，以对第一和第二多个存储器单元的存储器单元进行数字信号。还公开了其他实施例。

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