专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US4931709A NC unit processing method 失效
标题翻译： NC单元处理方法
公开(公告)号：US4931709A
公开(公告)日：1990-06-05
申请号：US141598
申请日：1987-12-03
申请人： Yoshiaki Ikeda , Mitsuru Kuwasawa
发明人： Yoshiaki Ikeda , Mitsuru Kuwasawa
IPC分类号： G05B19/18 , G05B19/414
CPC分类号： G05B19/4147 , G05B2219/34287 , G05B2219/34367 , G05B2219/36499
摘要： An NC unit processing method executes numerical control processing based on a numerical control program and sequence control processing based on a sequence program at predetermined times on a time-sharing basis. The processing method first stores a location of a sequence program to be executed next in a predetermined storage area in response to a first timer interrupt (IRQ.sub.n+1) generated during execution of the sequence program. Input/output processing based on an input/output program is then executed, followed by numerical control processing based on the numerical control program in response to a second timer interrupt (IRQ.sub.n) generated during execution of the input/output processing. When the numerical control program ends, the execution location of the sequence program is referred to, and sequence program processing is executed from this location until the first timer interrupt (IRQ.sub.n) is once again generated.

2. 发明授权

US5168442A Programmable controller with modifiable ladder program 失效
标题翻译：具有可修改梯形图程序的可编程控制器
公开(公告)号：US5168442A
公开(公告)日：1992-12-01
申请号：US460100
申请日：1990-02-09
申请人： Yoshiaki Ikeda , Mitsuru Kuwasawa
发明人： Yoshiaki Ikeda , Mitsuru Kuwasawa
IPC分类号： G05B19/05 , G05B19/414
CPC分类号： G05B19/056 , G05B19/4147 , G05B2219/36108
摘要： A programmable controller according to the present invention is for reinforcing the function of a programmable machine controller (PMC) of a numerical control unit (CNC) incorporating a minicomputer. In order to achieve high-speed processing of a PMC ladder program which implements auxiliary control functions for machining inclusive of tool-change control, control of the rotational speed of a spindle and workpiece-change control, the programmable controller is provided with an electrically rewritable programmable read-only memory (EEPROM) (6), and a random-access memory (RAM) (7) to which program data is transferred from the EEPROM (6), and the arrangement is such that the contents of the EEPROM (6) are rewritten before the data transfer.
摘要翻译： PCT No.PCT / JP89 / 00610 Sec。 371日期1990年2月9日 102（e）1990年2月9日PCT PCT 1991年6月19日PCT公布。出版物WO90 / 00763 1990年1月25日。根据本发明的可编程控制器用于加强结合小型计算机的数控单元（CNC）的可编程机器控制器（PMC）的功能。为了实现PMC梯形图程序的高速处理，其实现了包括刀具更换控制在内的加工辅助控制功能，控制主轴转速和工件更换控制，可编程控制器具有电可重写可编程只读存储器（EEPROM）（6）和从EEPROM（6）向其传送程序数据的随机存取存储器（RAM）（7），并且所述EEPROM（6）的内容）在数据传输之前被重写。

3. 发明授权

US4908555A Axis feedrate output system 失效
标题翻译：轴进给速度输出系统
公开(公告)号：US4908555A
公开(公告)日：1990-03-13
申请号：US273517
申请日：1988-11-02
申请人： Yoshiaki Ikeda , Mitsuru Kuwasawa
发明人： Yoshiaki Ikeda , Mitsuru Kuwasawa
IPC分类号： G05B19/416
CPC分类号： G05B19/416
摘要： An axis feedrate output system for CNC equipment which controls the position of a machining table in each axis by effecting feedrate control in accordance with a residual error between a position command and detected positional information in each axis. A current feedrate of the machining table in each axis is derived from the residual error, and a current actual feedrate of the machining table is synthesized using the current feedrate for the respective axes an output which represents the current actual feedrate of the machining table in the form of a ratio to a predetermined maximum feedrate is generated. An error register stores the residual error (servo error) between the position command for each axis from an MPU in the CNC equipment and the positional information detected by a position sensor and provides a feedrate command for effecting feedrate control. A fixed relationship between the residual error and the current feedrate in each axis is utilized to obtain the current feedrate in each axis from the residual error.

4. 发明授权

US5070288A Reference point return system 失效
标题翻译：参考点返回系统
公开(公告)号：US5070288A
公开(公告)日：1991-12-03
申请号：US476416
申请日：1990-05-31
申请人： Yoshiaki Ikeda , Mitsuru Kuwasawa , Kenichi Ito
发明人： Yoshiaki Ikeda , Mitsuru Kuwasawa , Kenichi Ito
IPC分类号： G05B19/18 , G05B19/401 , G05B19/414 , G05D3/12
CPC分类号： G05B19/4144 , G05B19/4015 , G05B2219/50025
摘要： A system for carrying out reference point return in a numerical control device is provided, including a deceleration dog having a short length and arranged at a machine table, a deceleration limit switch operated by the deceleration dog, for generating a deceleration start signal, and a time setting device (6) for setting a deceleration time, starting with a generation of the deceleration start signal and ending with a generation of a deceleration end signal, and a slow-speed travel time. A reference point return processing device (5) starts a deceleration of the machine table in response to the deceleration start signal, and stops the machine table at a first electrical grid point reached by the machine table after the slow-speed travel time has elapsed after the passing of the deceleration time.
摘要翻译： PCT No.PCT / JP89 / 00998 Sec。 371日期1990年5月31日第 102（e）日期1990年5月31日PCT提交1989年9月29日PCT公布。出版物WO90 / 04815 日期为1990年5月3日。一种用于在数控装置中进行基准点返回的系统，其特征在于，具备长度较短的减速齿轮，设置在机台上，由所述减速齿轮操作的减速限制开关，减速开始信号，以及用于设定减速时间的时间设定装置（6），从生成减速开始信号开始并以减速结束信号的生成结束，以及慢速行驶时间。参考点返回处理装置（5）响应于减速开始信号开始机床的减速，并且在经过慢速行驶时间之后经过机床表达到的第一电网点停止机台，经过通过减速时间。

5. 发明授权

US4682167A Data transfer system for numerically controlled equipment 失效
公开(公告)号：US4682167A
公开(公告)日：1987-07-21
申请号：US822422
申请日：1986-01-16
申请人： Yoshiaki Ikeda , Mitsuru Kuwasawa
发明人： Yoshiaki Ikeda , Mitsuru Kuwasawa
IPC分类号： H04L29/08 , G05B19/414 , G06F12/04 , G06F13/42 , H04Q9/00 , G06F13/00 , H04L13/00
CPC分类号： G06F13/4243 , G05B19/414 , G06F13/4239 , G05B2219/33182
摘要： A data transfer system transfers, bit by bit, serial data sent from first equipment (10) to predetermined bits of a predetermined address in a RAM (300) of second equipment (30). Each bit of the serial data sent from the first equipment (10) is transferred to a predetermined bit of a predetermined address of the RAM (300) in the second equipment (20) upon each occurrence of a clock pulse which is delivered from the first equipment (10) in synchronism with each bit data. The data transfer system includes a counter (206) which is incremented by the clock pulses and an address generator (210) which responds to the output of the counter (206) to generate an address of the RAM (300). A bit address generator (211) responds to the output of the counter (206) to generate a bit address for specifying a bit position in one address of the RAM (300), and a timing control circuit (209) responds to the output of the counter (206) to generate timing signals for a read cycle and a write cycle succeeding it during the period of generation of one address by the address generator (210). A read modify write circuit (214) substitutes bit data from the first equipment 10 for data at that bit position of a plurality of bits in parallel data corresponding to the address from the address generator (210), read out of the RAM (300) in the read cycle specified by the timing control circuit (209), which is specified by the bit address from the bit address generator (211). The substituted parallel data is transferred to the original address in the RAM (300) during the write cycle specified by the timing control circuit (209). Thus, each bit of the serial data sent from the first equipment (10) can be transferred to a predetermined bit of a predetermined address in the RAM (300) of the second equipment (30).

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式