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1. 发明授权

US08416005B2 Multifunctional output drivers and multifunctional transmitters using the same 有权
标题翻译：多功能输出驱动器和使用相同功能的多功能变送器
公开(公告)号：US08416005B2
公开(公告)日：2013-04-09
申请号：US12917894
申请日：2010-11-02
申请人： Yan-Bin Luo , Tun-Shih Chen , Min-Chung Chou
发明人： Yan-Bin Luo , Tun-Shih Chen , Min-Chung Chou
IPC分类号： H03L5/00
CPC分类号： H03K19/018528 , H04L25/0272 , H04L25/028
摘要： A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.
摘要翻译：提供能够以不同模式发送不同接口的信号的多功能输出驱动器，其中提供第一和第二电流源，并且第一至第四开关器件耦合在第一和第二电流源之间，第一和第二电流源并且第一至第四开关装置用作电流转向电路。在第一传输模式中，第一和第二开关器件被关断，并且第三和第四开关器件和第一电流源用作电流模式逻辑电路，以根据输入提供与第一传输接口兼容的输出信号来自前驱动器的信号。在第二传输模式中，当前转向电路根据来自预驱动器的输入信号输出与第二传输接口兼容的输出信号。

2. 发明申请

US20130049830A1 DELAY LOCK LOOP CIRCUIT 有权
标题翻译：延时锁定电路
公开(公告)号：US20130049830A1
公开(公告)日：2013-02-28
申请号：US13217293
申请日：2011-08-25
申请人： Min-Chung Chou
发明人： Min-Chung Chou
IPC分类号： H03L7/06
CPC分类号： H03L7/0812
摘要： The invention provides a delay lock loop circuit (DLL) for generating a locked signal, the DLL circuit includes: a phase detector, a first and a second voltage controlled delay chains, a charge pump and a duty cycle detection pump. The phase detector generates a phase detecting result by detecting a phase difference between the clock signal and the locked signal. The first and the second voltage controlled delay chains generate a first and a second delayed signals by delaying the clock signal according to the first and the second control signals, respectively. The charge pump is used for generating the first and the second control signal according to the phase detecting result. The duty cycle detection pump is used for controlling a voltage level of the second control signal according to the first and the second delayed signals.
摘要翻译：本发明提供一种用于产生锁定信号的延迟锁定环电路（DLL），该DLL电路包括：相位检测器，第一和第二压控延时链，电荷泵和占空比检测泵。相位检测器通过检测时钟信号和锁定信号之间的相位差来产生相位检测结果。第一和第二电压控制延迟链通过分别根据第一和第二控制信号延迟时钟信号而产生第一和第二延迟信号。电荷泵用于根据相位检测结果产生第一和第二控制信号。占空比检测泵用于根据第一和第二延迟信号来控制第二控制信号的电压电平。

3. 发明授权

US08149907B2 Adaptive equalization apparatus with equalization parameter setting adaptively adjusted according to edges of equalizer output monitored in real-time manner and related method thereof 有权
标题翻译：具有根据实时监控的均衡器输出边缘自适应调整的均衡参数设置的自适应均衡装置及其相关方法
公开(公告)号：US08149907B2
公开(公告)日：2012-04-03
申请号：US12350193
申请日：2009-01-07
申请人： Min-Chung Chou
发明人： Min-Chung Chou
IPC分类号： H03H7/40
CPC分类号： H04L7/0058 , H03K9/08 , H04L25/03019
摘要： An adaptive equalization apparatus is provided. The adaptive equalization apparatus includes an equalizer, a monitor circuit, and a control circuit. The equalizer receives a first signal, and equalizes the first signal according to an equalization parameter setting to thereby generate a second signal. The monitor circuit is electrically connected to the equalizer, and monitors edges of the second signal in a real-time manner to thereby generate a detection result. The control logic is electrically connected to the equalizer, and adaptively adjusts the equalization parameter setting according to the detection result.
摘要翻译：提供一种自适应均衡装置。自适应均衡装置包括均衡器，监视电路和控制电路。均衡器接收第一信号，并根据均衡参数设置对第一信号进行均衡，从而产生第二信号。监视电路电连接到均衡器，并且以实时的方式监视第二信号的边缘，从而产生检测结果。控制逻辑电连接到均衡器，并且根据检测结果自适应地调整均衡参数设置。

4. 发明授权

US08081530B2 Semiconductor memory device and associated local sense amplifier 有权
标题翻译：半导体存储器件和相关本地读出放大器
公开(公告)号：US08081530B2
公开(公告)日：2011-12-20
申请号：US12713639
申请日：2010-02-26
申请人： Min Chung Chou
发明人： Min Chung Chou
IPC分类号： G11C7/02
CPC分类号： G11C7/065 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C11/4094 , G11C11/4096 , G11C2207/002
摘要： A semiconductor memory device comprises a plurality of memory cells, a bit line sense amplifier, a local sense amplifier, and a sense amplifier. The memory cells are connected between a word line and a bit line pair, and the bit line sense amplifier is configured to amplify voltages of data from the bit line pair and then transmits the data to a local data line pair. The local sense amplifier is configured to amplify voltages of the data from the local data line pair and transmit the data to a global data line pair in response to first and second control signals, and the sense amplifier is configured to amplify the voltages of the data from the global data line pair and transmit the data to an input/output line pair during a read operation. The local sense amplifier comprises a first read circuit, a second read circuit, and a write circuit, and when the memory device performs the read operation, the data is transmitted from the first read circuit to the write circuit via the second read circuit.
摘要翻译：半导体存储器件包括多个存储器单元，位线读出放大器，局部读出放大器和读出放大器。存储单元连接在字线和位线对之间，位线读出放大器被配置为放大来自位线对的数据电压，然后将数据发送到本地数据线对。本地感测放大器被配置为放大来自本地数据线对的数据的电压，并且响应于第一和第二控制信号将数据发送到全局数据线对，并且读出放大器被配置为放大数据的电压从全局数据线对，并在读取操作期间将数据传输到输入/输出线对。本地读出放大器包括第一读取电路，第二读取电路和写入电路，并且当存储器件执行读取操作时，数据经由第二读取电路从第一读取电路传输到写入电路。

5. 发明申请

US20110227624A1 DUTY CYCLE CORRECTION CIRCUIT 有权
标题翻译：占空比校正电路
公开(公告)号：US20110227624A1
公开(公告)日：2011-09-22
申请号：US12728812
申请日：2010-03-22
申请人： MIN CHUNG CHOU
发明人： MIN CHUNG CHOU
IPC分类号： H03K3/017
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.
摘要翻译：占空比校正电路包括第一和第二脉冲发生器，时钟分频单元，检测单元和脉冲宽度控制单元。第一脉冲发生器被配置为与第一时钟信号的第一边沿同步地产生第一脉冲信号的第一边缘，并且第二脉冲发生器被配置为与第二脉冲信号的第二边沿同步地产生第二脉冲信号的第一边缘边缘的第一个脉冲信号。时钟分频单元被配置为通过划分第一时钟信号的频率来产生第二时钟信号。检测单元被配置为根据第二时钟信号和第一脉冲信号的第一边缘与第二脉冲信号的第二边沿之间的时间间隔产生检测信号。特别地，第一和第二脉冲信号的脉冲宽度相同并且可以根据来自脉冲宽度控制单元的控制信号来调节。

6. 发明授权

US08018262B1 Duty cycle correction circuit 有权
标题翻译：占空比校正电路
公开(公告)号：US08018262B1
公开(公告)日：2011-09-13
申请号：US12728812
申请日：2010-03-22
申请人： Min Chung Chou
发明人： Min Chung Chou
IPC分类号： H03K3/017 , H03K5/04 , H03K7/08
CPC分类号： H03K5/1565
摘要： A duty cycle correction circuit comprises first and second pulse generators, a clock dividing unit, a detecting unit, and a pulse width control unit. The first pulse generator is configured to generate a first edge of a first pulse signal in synchronization with a first edge of a first clock signal, and the second pulse generator is configured to generate a first edge of a second pulse signal in synchronization with a second edge of the first pulse signal. The clock dividing unit is configured to generate a second clock signal by dividing the frequency of the first clock signal. The detecting unit is configured to generate a detecting signal according to the second clock signal and a time interval between the first edge of the first pulse signal and a second edge of the second pulse signal. In particular, pulse widths of the first and second pulse signals are the same and are adjustable according to a control signal from the pulse width control unit.
摘要翻译：占空比校正电路包括第一和第二脉冲发生器，时钟分频单元，检测单元和脉冲宽度控制单元。第一脉冲发生器被配置为与第一时钟信号的第一边沿同步地产生第一脉冲信号的第一边缘，并且第二脉冲发生器被配置为与第二脉冲信号的第二边沿同步地产生第二脉冲信号的第一边缘边缘的第一个脉冲信号。时钟分频单元被配置为通过划分第一时钟信号的频率来产生第二时钟信号。检测单元被配置为根据第二时钟信号和第一脉冲信号的第一边缘与第二脉冲信号的第二边沿之间的时间间隔产生检测信号。特别地，第一和第二脉冲信号的脉冲宽度相同并且可以根据来自脉冲宽度控制单元的控制信号来调节。

7. 发明申请

US20110211417A1 MEMORY DEVICE WITH PSEUDO DOUBLE CLOCK SIGNALS AND THE METHOD USING THE SAME 有权
标题翻译：具有PSEUDO双重时钟信号的存储器件和使用其的方法
公开(公告)号：US20110211417A1
公开(公告)日：2011-09-01
申请号：US12713561
申请日：2010-02-26
申请人： MIN CHUNG CHOU
发明人： MIN CHUNG CHOU
IPC分类号： G11C8/18
CPC分类号： G11C7/222
摘要： A method for operating a memory device with pseudo double clock signals comprises the steps of: generating an even clock signal and an odd clock signal, wherein the clock rates of both the even clock signal and the odd clock signal are half that of the input clock signal, and the even clock signal is the inverse signal of the odd clock signal; if the logic level of the even clock signal is 1 when receiving a trigger of a control signal, applying the even clock signal to a memory device; and if the logic level of the odd clock signal is 1 when receiving another trigger of the control signal, applying the odd clock signal to the memory device.
摘要翻译：一种使用伪双时钟信号操作存储器件的方法包括以下步骤：产生偶数时钟信号和奇数时钟信号，其中偶数时钟信号和奇数时钟信号的时钟速率是输入时钟的时钟速率的一半信号，偶数时钟信号是奇数时钟信号的反相信号; 如果当接收到控制信号的触发时偶数时钟信号的逻辑电平为1，则将偶数时钟信号施加到存储器件; 并且如果在接收到控制信号的另一个触发时奇数时钟信号的逻辑电平为1，则将奇数时钟信号施加到存储器件。

8. 发明授权

US07965121B2 Multifunctional output drivers and multifunctional transmitters using the same 失效
标题翻译：多功能输出驱动器和使用相同功能的多功能变送器
公开(公告)号：US07965121B2
公开(公告)日：2011-06-21
申请号：US12188335
申请日：2008-08-08
申请人： Yan-Bin Luo , Tun-Shih Chen , Min-Chung Chou
发明人： Yan-Bin Luo , Tun-Shih Chen , Min-Chung Chou
IPC分类号： H03L5/00
CPC分类号： H03K19/018528 , H04L25/0272 , H04L25/028
摘要： A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.
摘要翻译：提供能够以不同模式发送不同接口的信号的多功能输出驱动器，其中提供第一和第二电流源，并且第一至第四开关器件耦合在第一和第二电流源之间，第一和第二电流源并且第一至第四开关装置用作电流转向电路。在第一传输模式中，第一和第二开关器件被关断，并且第三和第四开关器件和第一电流源用作电流模式逻辑电路，以根据输入提供与第一传输接口兼容的输出信号来自前驱动器的信号。在第二传输模式中，当前转向电路根据来自预驱动器的输入信号输出与第二传输接口兼容的输出信号。

9. 发明授权

US07741889B2 Phase locked loop with phase rotation for spreading spectrum 失效
标题翻译：具有相位旋转的锁相环用于扩展频谱
公开(公告)号：US07741889B2
公开(公告)日：2010-06-22
申请号：US12010463
申请日：2008-01-25
申请人： Min-Chung Chou
发明人： Min-Chung Chou
IPC分类号： H03L7/06
CPC分类号： H03L7/081 , H03L7/0995
摘要： A phase locked loop (PLL) with phase rotation spreading includes a phase detector, a charge pump, a filter, a voltage controlled oscillator (VCO) and a selector. The phase detector receives a reference clock signal and a feedback clock signal to thereby produce an error signal. The charge pump converts the error signal into a current signal. The filter converts the current signal into a voltage signal. The VCO produces N clock signals with a same frequency in accordance with the voltage signal, where the N clock signals have phases θ0 to θN-1 respectively, and θj indicates a lead of 2π/N over θj+1, for j=0, 1, . . . , N−2. The selector selects one from the N clock signals in accordance with a predetermined sequence to thereby produce a target clock signal, and finely adjusts a frequency of the target clock signal for a spreading operation.
摘要翻译：具有相位旋转扩展的锁相环（PLL）包括相位检测器，电荷泵，滤波器，压控振荡器（VCO）和选择器。相位检测器接收参考时钟信号和反馈时钟信号，从而产生误差信号。电荷泵将误差信号转换为电流信号。滤波器将电流信号转换为电压信号。 VCO根据电压信号产生具有相同频率的N个时钟信号，其中N个时钟信号具有相位和角度;分别为0至＆amp; The; N-1，＆amp; the; s表示2＆pgr / N超过的导数; j + 1，对于j = 0，1，... 。。，N-2。选择器根据预定的顺序从N个时钟信号中选择一个，从而产生目标时钟信号，并且精细地调整用于扩展操作的目标时钟信号的频率。

10. 发明申请

US20090174439A1 MULTIFUNCTIONAL OUTPUT DRIVERS AND MULTIFUNCTIONAL TRANSMITTERS USING THE SAME 失效
标题翻译：多功能输出驱动器和使用该功能的多功能发射器
公开(公告)号：US20090174439A1
公开(公告)日：2009-07-09
申请号：US12188335
申请日：2008-08-08
申请人： Yan-Bin LUO , Tun-Shih CHEN , Min-Chung CHOU
发明人： Yan-Bin LUO , Tun-Shih CHEN , Min-Chung CHOU
IPC分类号： H03K3/00
CPC分类号： H03K19/018528 , H04L25/0272 , H04L25/028
摘要： A multifunctional output driver capable of transmitting signals of different interfaces in different modes is provided, in which first and second current sources are provided, and first to fourth switching devices are coupled between the first and second current sources, and the first and second current source and the first to the fourth switching devices act as a current steering circuit. In a first transmission mode, the first and second switching devices are turned off, and the third and fourth switching devices and the first current source act as a current mode logic circuit to provide an output signal compatible with a first transmission interface according to an input signal from a pre-driver. In a second transmission mode, the current steering circuit outputs an output signal compatible with a second transmission interface according to the input signal from the pre-driver.
摘要翻译：提供能够以不同模式发送不同接口的信号的多功能输出驱动器，其中提供第一和第二电流源，并且第一至第四开关器件耦合在第一和第二电流源之间，第一和第二电流源并且第一至第四开关装置用作电流转向电路。在第一传输模式中，第一和第二开关器件被关断，并且第三和第四开关器件和第一电流源用作电流模式逻辑电路，以根据输入提供与第一传输接口兼容的输出信号来自前驱动器的信号。在第二传输模式中，当前转向电路根据来自预驱动器的输入信号输出与第二传输接口兼容的输出信号。

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