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    • 6. 发明授权
    • Semiconductor device
    • 半导体器件
    • US08179179B2
    • 2012-05-15
    • US12881541
    • 2010-09-14
    • Min-Su ParkHoon Choi
    • Min-Su ParkHoon Choi
    • H03H11/16
    • H03L7/0812G11C7/222
    • A semiconductor device includes a reset signal generator configured to change the number of activated signals among a plurality of reset signals according to a frequency of an external clock, a plurality of mixing control signal generators configured to generate a plurality of first and second mixing control signals, and a clock mixer configured to generate a mixing clock by mixing a first driving clock and a second driving clock, wherein the first driving clock is generated by driving a positive clock of the external clock according to the plurality of first mixing control signals, and the second driving clock is generated by driving a negative clock of the external clock according to the plurality of second mixing control signals.
    • 半导体器件包括:复位信号发生器,被配置为根据外部时钟的频率改变多个复位信号中的激活信号数;多个混合控制信号发生器,被配置为产生多个第一和第二混合控制信号 以及时钟混频器,被配置为通过混合第一驱动时钟和第二驱动时钟来产生混频时钟,其中通过根据多个第一混频控制信号驱动外部时钟的正时钟来产生第一驱动时钟,以及 通过根据多个第二混合控制信号驱动外部时钟的负时钟来产生第二驱动时钟。
    • 7. 发明申请
    • DELAY LOCKED LOOP CIRCUIT AND INTEGRATED CIRCUIT INCLUDING THE SAME
    • 延迟锁定环路电路和集成电路,包括它们
    • US20120007645A1
    • 2012-01-12
    • US12981256
    • 2010-12-29
    • Min-Su PARKHoon Choi
    • Min-Su PARKHoon Choi
    • H03L7/06
    • H03L7/0814
    • A delay locked loop (DLL) circuit includes a timing pulse generating unit configured to generate a plurality of timing pulses, which are sequentially pulsed during delay shifting update periods, in response to a source clock, wherein the number of the generated timing pulses changes according to a frequency of the source clock; a clock delay unit configured to compare a phase of the source clock with a phase of a feedback clock at a time point defined by each of the timing pulses, and delay a phase of an internal clock, corresponding to a rising or falling edge of the source clock, according to the comparison result; and a delay replica modeling unit configured to reflect actual delay conditions of the internal clock path on an output clock of the clock delay unit, and to output the feedback clock.
    • 延迟锁定环(DLL)电路包括定时脉冲发生单元,其被配置为响应于源时钟而在延迟移位更新周期期间产生顺序脉冲的多个定时脉冲,其中所产生的定时脉冲的数量根据 到源时钟的频率; 时钟延迟单元,被配置为将源时钟的相位与由每个定时脉冲定义的时间点的反馈时钟的相位进行比较,并且延迟对应于所述定时脉冲的上升沿或下降沿的内部时钟的相位 源时钟,根据比较结果; 以及延迟复制模型单元,被配置为反映所述时钟延迟单元的输出时钟上的内部时钟路径的实际延迟条件,并输出所述反馈时钟。
    • 9. 发明授权
    • Image forming apparatus and method to operatively control the same
    • 图像形成装置及其操作方法
    • US07824006B2
    • 2010-11-02
    • US11680808
    • 2007-03-01
    • Min-su Park
    • Min-su Park
    • B41J2/165
    • B41J2/16526B41J2/16535B41J2/16585
    • An image forming apparatus and method to operatively control the same. The apparatus includes an ink cartridge having a plurality of print heads arranged in a widthwise direction of a print medium, a wiping unit to wipe the print heads while moving in the print medium feeding direction, a positional information providing unit to provide positional information about a position of the wiping unit, and a controller to operatively control the print heads. The controller controls the print heads that, on the basis of the positional information provided and offset information of the ink cartridge, the controller estimates a wiping timing to wipe the nozzles of the print heads with the wiping unit and determines a spitting timing to eject a predetermined amount of ink in the wiped sequence of the nozzles, whereby that the wiping and spitting operations are performed at the estimated wiping timing and the determined spitting timing.
    • 一种可操作地控制该图像形成装置和方法。 该装置包括具有沿打印介质的宽度方向布置的多个打印头的墨盒,在打印介质进给方向移动时擦拭打印头的擦拭单元,提供关于打印介质的位置信息的位置信息提供单元 擦拭单元的位置,以及可操作地控制打印头的控制器。 控制器控制打印头,根据提供的位置信息和墨盒的偏移信息,控制器估计擦拭时间,以便用擦拭单元擦拭打印头的喷嘴,并且确定吐出时间 在喷嘴的擦拭序列中预定量的墨水,从而在估计的擦拭定时和所确定的吐痰时间执行擦拭和吐痰操作。