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1. 发明申请

US20070025380A1 PACKET PROCESSING APPARATUS, PACKET PROCESSING METHOD, AND PACKET EXCHANGE 有权
标题翻译：分组处理设备，分组处理方法和分组交换
公开(公告)号：US20070025380A1
公开(公告)日：2007-02-01
申请号：US11537272
申请日：2006-09-29
申请人： Tatsuhiko AMAGAI , Mikiharu YAMASHITA , Tatsuo ARAMIZU
发明人： Tatsuhiko AMAGAI , Mikiharu YAMASHITA , Tatsuo ARAMIZU
IPC分类号： H04L12/54 , H04J3/16
CPC分类号： H04L12/5601 , H04L2012/5658 , H04L2012/5667
摘要： A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.
摘要翻译：公开了一种用于通过多个层交换分组数据的分组处理方法，包括以下步骤：将整个分组存储到分组存储器; 并且将在多层的层2处理部分和层3处理部分的处理中使用的分组数据的每个分组的一部分存储到多端口共享存储器，层2处理部分和层3处理部分访问多端口共享内存的内存空间相同。此外，使用流水线处理系统，使得当层2处理部分和层3处理部分访问共享存储器时，它们不彼此干扰。

2. 发明授权

US6105160A Packet error detecting device in a DMA transfer 失效
标题翻译： DMA传输中的数据包错误检测设备
公开(公告)号：US6105160A
公开(公告)日：2000-08-15
申请号：US995862
申请日：1997-12-22
申请人： Keisuke Fukumoto , Mikiharu Yamashita
发明人： Keisuke Fukumoto , Mikiharu Yamashita
IPC分类号： G06F13/00 , G06F11/10 , H03M13/00 , H03M13/09 , H03M13/11 , H03M13/27 , H04L1/00
CPC分类号： H03M13/373 , H03M13/098 , H03M13/11 , H03M13/27
摘要： A packet error detecting device for detecting the existence of an error of the packet data transferred by a packet switching in a DMA transfer, comprising an operation unit formed by hardware for executing a necessary operation to detect a packet error in the packet data received in every block, a DMA controller for DMA transferring data from a memory storing the received data to the operation unit, previous to the DMA transfer of the data toward an external device, and a CPU for performing an error procedure if detecting a packet error as the result of the error detection by the operation unit.
摘要翻译：一种分组错误检测装置，用于检测通过DMA传输中的分组交换传送的分组数据的错误的存在，包括由硬件形成的操作单元，用于执行必要的操作，以检测每个接收到的分组数据中的分组错误块，用于在从存储接收到的数据的存储器中将数据传送到操作单元的DMA控制器之前，向数据向外部设备的DMA传送;以及用于执行错误过程的CPU，如果检测到数据包错误作为结果由操作单元进行错误检测。

3. 发明授权

US08040821B2 Switching device, switching method, and switch control program 有权
标题翻译：开关装置，开关方式和开关控制程序
公开(公告)号：US08040821B2
公开(公告)日：2011-10-18
申请号：US11915699
申请日：2006-06-02
申请人： Junichi Higuchi , Youichi Hidaka , Mikiharu Yamashita , Yukihiro Hara
发明人： Junichi Higuchi , Youichi Hidaka , Mikiharu Yamashita , Yukihiro Hara
IPC分类号： H04L12/28 , H04L12/50 , H04Q11/00
CPC分类号： H04L49/254 , H04L49/1546 , H04L49/3018 , H04L49/3027 , H04Q3/52 , H04Q2213/1301 , H04Q2213/1302 , H04Q2213/1304
摘要： A switching device includes an input stage switch group 1-1 including a plurality of input lines, an output stage switch group 1-3 including a plurality of output lines, an intermediate stage switch group 1-2 arranged between the input stage switch group and the output stage switch group, and a scheduler 1-22 deciding a signal path of each of intermediate stage switches 1-21 in the intermediate stage switch group based on information input to the respective input lines. The intermediate stage switch group is divided into a plurality of groups, a plurality of the schedulers is arranged in a distributed fashion to correspond to the plurality of groups, respectively and the schedulers operate independently of one another.
摘要翻译：开关装置包括：输入级开关组1-1，其包括多条输入线;输出级开关组1-3，包括多条输出线;中间级开关组1-2，配置在输入级开关组和输出级开关组，以及调度器1-22，基于输入到各输入线的信息，决定中间级交换机组中的每个中间级交换机1-21的信号路径。中间级交换机组被分成多个组，多个调度器以分布的方式分别对应于多个组，并且调度器彼此独立地操作。

4. 发明授权

US6147999A ATM switch capable of routing IP packet 有权
标题翻译： ATM交换机能够路由IP包
公开(公告)号：US6147999A
公开(公告)日：2000-11-14
申请号：US321241
申请日：1999-05-27
申请人： Masahiko Honda , Mikiharu Yamashita
发明人： Masahiko Honda , Mikiharu Yamashita
IPC分类号： H04Q3/00 , H04M11/00 , H04L12/28
CPC分类号： H04M11/002
摘要： Disclosed is an ATM switch which comprises: an ATM switch unit; a switch control unit for controlling the ATM switch unit; one or more circuit accommodation units for connecting the switch with one or more external ATM networks, respectively, and an IP routing process unit for routing IP packets in a form of ATM cells. In the ATM switch, the IP routing process unit may comprise: a cell storage unit having a plurality of memories; a distributing means for distributing the ATM cells received from the ATM switch unit to the plurality of memories while grouping the ATM cells into each of the plurality of memories in accordance with an IP packet to which each of the ATM cells belongs; sending means for sending all the ATM cells belonging to an identical IP packet when the all the ATM cells belonging to the identical IP packet have been stored in respective one of the plurality of memories; and means for converting VPI/VCI (Virtual Path Identifier/ Virtual Channel Identifier) of the all the ATM cells belonging to the identical IP packet.
摘要翻译：公开了一种ATM交换机，其包括：ATM交换单元; 开关控制单元，用于控制ATM开关单元; 分别用于将交换机与一个或多个外部ATM网络连接的一个或多个电路调节单元和用于以ATM信元的形式路由IP分组的IP路由处理单元。在ATM交换机中，IP路由处理单元可以包括：具有多个存储器的单元存储单元; 分配装置，用于根据每个ATM信元所属的IP分组，将从ATM交换单元接收的ATM信元分配到多个存储器，同时将ATM信元分组成多个存储器; 发送装置，用于当属于相同IP分组的所有ATM信元已经存储在多个存储器的相应一个存储器中时，发送属于相同IP分组的所有ATM信元; 以及用于转换属于相同IP分组的所有ATM信元的VPI / VCI（虚拟路径标识符/虚拟信道标识符）的装置。

5. 发明授权

US07970012B2 Packet processing using a multi-port memory 失效
标题翻译：使用多端口存储器进行数据包处理
公开(公告)号：US07970012B2
公开(公告)日：2011-06-28
申请号：US12395051
申请日：2009-02-27
申请人： Tatsuhiko Amagai , Mikiharu Yamashita , Tatsuo Aramizu
发明人： Tatsuhiko Amagai , Mikiharu Yamashita , Tatsuo Aramizu
IPC分类号： H04J3/16 , H04J3/22
CPC分类号： H04L12/5601 , H04L2012/5658 , H04L2012/5667
摘要： A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.
摘要翻译：公开了一种用于通过多个层交换分组数据的分组处理方法，包括以下步骤：将整个分组存储到分组存储器; 并且将在多层的层2处理部分和层3处理部分的处理中使用的分组数据的每个分组的一部分存储到多端口共享存储器，层2处理部分和层3处理部分访问多端口共享内存的内存空间相同。此外，使用流水线处理系统，使得当层2处理部分和层3处理部分访问共享存储器时，它们不彼此干扰。

6. 发明授权

US07515610B2 Packet processing using a multi-port memory 有权
标题翻译：使用多端口存储器进行数据包处理
公开(公告)号：US07515610B2
公开(公告)日：2009-04-07
申请号：US11537272
申请日：2006-09-29
申请人： Tatsuhiko Amagai , Mikiharu Yamashita , Tatsuo Aramizu
发明人： Tatsuhiko Amagai , Mikiharu Yamashita , Tatsuo Aramizu
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L12/5601 , H04L2012/5658 , H04L2012/5667
摘要： A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.
摘要翻译：公开了一种用于通过多个层交换分组数据的分组处理方法，包括以下步骤：将整个分组存储到分组存储器; 并且将在多层的层2处理部分和层3处理部分的处理中使用的分组数据的每个分组的一部分存储到多端口共享存储器，层2处理部分和层3处理部分访问多端口共享内存的内存空间相同。此外，使用流水线处理系统，使得当层2处理部分和层3处理部分访问共享存储器时，它们不彼此干扰。

7. 发明申请

US20090028140A1 SWITCHING DEVICE, SWITCHING METHOD, AND SWITCH CONTROL PROGRAM 有权
标题翻译：切换设备，切换方法和切换控制程序
公开(公告)号：US20090028140A1
公开(公告)日：2009-01-29
申请号：US11915699
申请日：2006-06-02
申请人： Junichi Higuchi , Youichi Hidaka , Mikiharu Yamashita , Yukihiro Hara
发明人： Junichi Higuchi , Youichi Hidaka , Mikiharu Yamashita , Yukihiro Hara
IPC分类号： H04L12/50 , H04L12/56 , H04Q3/52
CPC分类号： H04L49/254 , H04L49/1546 , H04L49/3018 , H04L49/3027 , H04Q3/52 , H04Q2213/1301 , H04Q2213/1302 , H04Q2213/1304
摘要： A switching device includes an input stage switch group 1-1 including a plurality of input lines, an output stage switch group 1-3 including a plurality of output lines, an intermediate stage switch group 1-2 arranged between the input stage switch group and the output stage switch group, and a scheduler 1-22 deciding a signal path of each of intermediate stage switches 1-21 in the intermediate stage switch group based on information input to the respective input lines. The intermediate stage switch group is divided into a plurality of groups, a plurality of the schedulers is arranged in a distributed fashion to correspond to the plurality of groups, respectively and the schedulers operate independently of one another.
摘要翻译：开关装置包括：输入级开关组1-1，其包括多条输入线;输出级开关组1-3，包括多条输出线;中间级开关组1-2，配置在输入级开关组和输出级开关组，以及调度器1-22，基于输入到各输入线的信息，决定中间级交换机组中的每个中间级交换机1-21的信号路径。中间级交换机组被分成多个组，多个调度器以分布的方式分别对应于多个组，并且调度器彼此独立地操作。

8. 发明授权

US07130312B1 Packet processing apparatus, packet processing method, and packet exchange 失效
标题翻译：分组处理装置，分组处理方法和分组交换
公开(公告)号：US07130312B1
公开(公告)日：2006-10-31
申请号：US09404313
申请日：1999-09-24
申请人： Tatsuhiko Amagai , Mikiharu Yamashita , Tatsuo Aramizu
发明人： Tatsuhiko Amagai , Mikiharu Yamashita , Tatsuo Aramizu
IPC分类号： H04L12/28 , H04L12/56
CPC分类号： H04L12/5601 , H04L2012/5658 , H04L2012/5667
摘要： A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.
摘要翻译：公开了一种用于通过多个层交换分组数据的分组处理方法，包括以下步骤：将整个分组存储到分组存储器; 并且将在多层的层2处理部分和层3处理部分的处理中使用的分组数据的每个分组的一部分存储到多端口共享存储器，层2处理部分和层3处理部分访问多端口共享内存的内存空间相同。此外，使用流水线处理系统，使得当层2处理部分和层3处理部分访问共享存储器时，它们不彼此干扰。

9. 发明授权

US06515998B1 Table data retrieving apparatus retrieving table in which reference data is stored by using retrieval key 失效
标题翻译：表数据检索装置检索表，其中使用检索关键字存储参考数据
公开(公告)号：US06515998B1
公开(公告)日：2003-02-04
申请号：US09441088
申请日：1999-11-16
申请人： Mikiharu Yamashita , Tatsuhiko Amagai , Tatsuo Aramizu
发明人： Mikiharu Yamashita , Tatsuhiko Amagai , Tatsuo Aramizu
IPC分类号： H04L1256
CPC分类号： H04L45/742 , H04L45/00 , H04L45/54 , Y10S707/99943
摘要： A table data retrieving apparatus comprises a plurality of tables in which a reference data is stored. Each table of said plurality of tables is allocated into any group of a plurality of groups. A management table stores a priority of said table. A data retrieving section selects a group based on the retrieving key by which the reference data is selected. The data retrieving section retrieves with the priority said table which is allocated into the selected group is stored.
摘要翻译：表数据检索装置包括存储参考数据的多个表。所述多个表的每个表被分配到多个组的任何组中。管理表存储所述表的优先级。数据检索部分基于选择参考数据的检索关键码选择一个组。数据检索部分以优先级检索分配给所选择的组的所述表被存储。

10. 发明申请

US20090161694A1 PACKET PROCESSING USING A MULTI-PORT MEMORY 失效
标题翻译：使用多端口存储器进行分组处理
公开(公告)号：US20090161694A1
公开(公告)日：2009-06-25
申请号：US12395051
申请日：2009-02-27
申请人： Tatsuhiko AMAGAI , Mikiharu YAMASHITA , Tatsuo ARAMIZU
发明人： Tatsuhiko AMAGAI , Mikiharu YAMASHITA , Tatsuo ARAMIZU
IPC分类号： H04J3/22
CPC分类号： H04L12/5601 , H04L2012/5658 , H04L2012/5667
摘要： A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.
摘要翻译：公开了一种用于通过多个层交换分组数据的分组处理方法，包括以下步骤：将整个分组存储到分组存储器; 并且将在多层的层2处理部分和层3处理部分的处理中使用的分组数据的每个分组的一部分存储到多端口共享存储器，层2处理部分和层3处理部分访问多端口共享内存的内存空间相同。此外，使用流水线处理系统，使得当层2处理部分和层3处理部分访问共享存储器时，它们不彼此干扰。

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