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1. 发明申请

US20050028070A1 Methods and apparatuses for variable length encoding 有权
标题翻译：用于可变长度编码的方法和装置
公开(公告)号：US20050028070A1
公开(公告)日：2005-02-03
申请号：US10924647
申请日：2004-08-23
申请人： Chien-Hsin Lin , Mushtag Sarwar , Mike Lai , Mitchell Oslick
发明人： Chien-Hsin Lin , Mushtag Sarwar , Mike Lai , Mitchell Oslick
IPC分类号： H03M7/42 , H03M13/00
CPC分类号： H03M7/42
摘要： Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.
摘要翻译：使用向量处理单元进行可变长度编码的方法和装置。在本发明的一个方面，一种由微处理器执行可变长度编码的方法包括：接收多个参数，所述多个参数中的每一个参数对应于多个符号之一，以进行可变长度编码; 从多个参数同时产生多个第一码字以分别表示多个符号; 生成表示所述多个第一码字的比特长度的多个长度; 并输出多个第一码字和多个长度; 其中响应于微处理器接收到单个指令执行上述操作。

2. 发明授权

US06707398B1 Methods and apparatuses for packing bitstreams 有权
标题翻译：用于打包比特流的方法和装置
公开(公告)号：US06707398B1
公开(公告)日：2004-03-16
申请号：US10280821
申请日：2002-10-24
申请人： Chien-Hsin Lin , Mushtaq Sarwar , Mike Lai , Alexei Ouzilevaski
发明人： Chien-Hsin Lin , Mushtaq Sarwar , Mike Lai , Alexei Ouzilevaski
IPC分类号： H03M740
CPC分类号： H03M7/40 , G06F9/30025 , G06F9/30036
摘要： Methods and apparatuses for concatenating codewords of variable lengths using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to pack bit streams of variable lengths including: receiving a first bit segment from a first vector register; receiving a second bit segment from a second vector register; determining whether or not the sum of the bit length of the first bit segment and the bit length of the second bit segment is larger than a required length; generating a third bit segment from the first and second bit segments; and outputting the third bit segment in a third vector register; where the above operations are performed in response to the microprocessor receiving a first single instruction. The third bit segment is generated from concatenating the first bit segment and a beginning portion of the second bit segment such that the bit length of the third bit segment is equal to the required length when the sum is larger than the required length; and the third bit segment is generated from concatenating the first and second bit segments when the sum is not larger than the required length.
摘要翻译：使用向量处理单元连接可变长度码字的方法和装置。在本发明的一个方面，一种用于由微处理器执行以包装可变长度的比特流的方法，包括：从第一向量寄存器接收第一比特段; 从第二向量寄存器接收第二位段; 确定所述第一位段的位长度和所述第二位段的位长度之和是否大于所需长度; 从所述第一和第二位段产生第三位段; 并在第三矢量寄存器中输出第三位分段; 其中响应于微处理器接收到第一单个指令执行上述操作。第三位段是从第一位段和第二位段的开始部分连接而产生的，使得当该和大于所需长度时，第三位段的位长度等于所需长度; 并且当和不大于所需长度时，通过连接第一和第二位段来生成第三位段。

3. 发明授权

US06781529B1 Methods and apparatuses for variable length encoding 有权
标题翻译：用于可变长度编码的方法和装置
公开(公告)号：US06781529B1
公开(公告)日：2004-08-24
申请号：US10280225
申请日：2002-10-24
申请人： Chien-Hsin Lin , Mushtaq Sarwar , Mike Lai , Mitchell Oslick
发明人： Chien-Hsin Lin , Mushtaq Sarwar , Mike Lai , Mitchell Oslick
IPC分类号： H03M700
CPC分类号： H03M7/42
摘要： Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.
摘要翻译：使用向量处理单元进行可变长度编码的方法和装置。在本发明的一个方面，一种由微处理器执行可变长度编码的方法包括：接收多个参数，所述多个参数中的每一个参数对应于多个符号中的一个可变长度编码; 从多个参数同时产生多个第一码字以分别表示多个符号; 生成表示所述多个第一码字的比特长度的多个长度; 并输出多个第一码字和多个长度; 其中响应于微处理器接收到单个指令执行上述操作。

4. 发明授权

US07343542B2 Methods and apparatuses for variable length encoding 有权
标题翻译：用于可变长度编码的方法和装置
公开(公告)号：US07343542B2
公开(公告)日：2008-03-11
申请号：US10924647
申请日：2004-08-23
申请人： Chien-Hsin Lin , Mushtaq Sarwar , Mike Lai , Mitchell Oslick
发明人： Chien-Hsin Lin , Mushtaq Sarwar , Mike Lai , Mitchell Oslick
IPC分类号： H03M13/00 , H03M7/00
CPC分类号： H03M7/42
摘要： Methods and apparatuses for variable length encoding using a vector processing unit. In one aspect of the invention, a method for execution by a microprocessor to perform variable length encoding includes: receiving a plurality of parameters, each of the plurality of parameters corresponding to one of a plurality of symbols to be variable length encoded; generating concurrently a plurality of first codewords from the plurality of parameters to represent respectively the plurality of symbols; generating a plurality of lengths representing respectively bit lengths of the plurality of first codewords; and outputting the plurality of first codewords and the plurality of lengths; where the above operations are performed in response to the microprocessor receiving a single instruction.
摘要翻译：使用向量处理单元进行可变长度编码的方法和装置。在本发明的一个方面，一种由微处理器执行可变长度编码的方法包括：接收多个参数，所述多个参数中的每一个参数对应于多个符号之一，以进行可变长度编码; 从多个参数同时产生多个第一码字以分别表示多个符号; 生成表示所述多个第一码字的比特长度的多个长度; 并输出多个第一码字和多个长度; 其中响应于微处理器接收到单个指令执行上述操作。

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