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1. 发明授权

US07262137B2 Dry etching process for compound semiconductors 有权
标题翻译：化学半导体的干蚀刻工艺
公开(公告)号：US07262137B2
公开(公告)日：2007-08-28
申请号：US10782723
申请日：2004-02-18
申请人： Jennifer Wang , Huai-Min Sheng , Mike Barsky
发明人： Jennifer Wang , Huai-Min Sheng , Mike Barsky
IPC分类号： H01L21/311
CPC分类号： H01L21/30621
摘要： Accordingly, this invention relates to an dry etching process for semiconductor wafers. More particularly, the present invention discloses a dry etching process including a halogen etchant (24) and a nitrogen gas (28) that selectively etches a compound semiconductor material (18) faster than the front-side metal layers (16A)(16B). Further, the dry etching process produces a vertical wall profile on compound semiconductor material (18) in both X (38) and Y (40) crystalline directions without undercutting the top of a via-opening.
摘要翻译：因此，本发明涉及用于半导体晶片的干蚀刻工艺。更具体地，本发明公开了一种干蚀刻工艺，其包括选择性地比化学半导体材料（18）比前侧金属层（16A）（16B）蚀刻更多的卤素蚀刻剂（24）和氮气（28））。此外，干蚀刻工艺在X（38）和Y（40）结晶方向上在化合物半导体材料（18）上产生垂直壁轮廓，而不会削弱通孔开口的顶部。

2. 发明授权

US07582518B2 High electron mobility transistor semiconductor device and fabrication method thereof 有权
标题翻译：高电子迁移率晶体管半导体器件及其制造方法
公开(公告)号：US07582518B2
公开(公告)日：2009-09-01
申请号：US11598817
申请日：2006-11-14
申请人： Linh Dang , Wayne Yoshida , Gerry Mei , Jennifer Wang , Po-Hsin Liu , Jane Lee , Weidong Liu , Mike Barsky , Rich Lai
发明人： Linh Dang , Wayne Yoshida , Gerry Mei , Jennifer Wang , Po-Hsin Liu , Jane Lee , Weidong Liu , Mike Barsky , Rich Lai
IPC分类号： H01L21/338
CPC分类号： H01L29/66462 , H01L21/28587 , H01L21/32139 , H01L29/42316
摘要： In a method of forming a semiconductor device on a semiconductor substrate (100), a photoresist layer (102) is deposited on the semiconductor substrate; a window (106) is formed in the photoresist layer (102) by electron beam lithography; a conformal layer (108) is deposited on the photoresist layer (102) and in the window (106); and substantially all of the conformal layer (108) is selectively removed from the photoresist layer (102) and a bottom portion of the window to form dielectric sidewalls (110) in the window (106).
摘要翻译：在半导体衬底（100）上形成半导体器件的方法中，在半导体衬底上沉积光致抗蚀剂层（102）通过电子束光刻在光致抗蚀剂层（102）中形成窗口（106）在光致抗蚀剂层（102）和窗口（106）中沉积共形层（108）; 并且基本上所有的保形层（108）从光致抗蚀剂层（102）和窗口的底部部分选择性地移除，以在窗口（106）中形成电介质侧壁（110）。

3. 发明申请

US20050181618A1 Polymer via etching process 审中-公开
标题翻译：聚合物通过蚀刻工艺
公开(公告)号：US20050181618A1
公开(公告)日：2005-08-18
申请号：US10781353
申请日：2004-02-17
申请人： Jennifer Wang , Mike Barsky
发明人： Jennifer Wang , Mike Barsky
IPC分类号： H01L21/311 , H01L21/768 , H01L21/4763 , H01L21/302 , H01L21/44 , H01L21/461
CPC分类号： H01L21/76804 , H01L21/31138 , H01L21/31144
摘要： An improved etching process for creating dimensionally accurate sub-micron and micron via-openings is disclosed. Specifically, this invention discloses a via etching process for a polymer layer (24) deposited on a semiconductor substrate (28) comprising the steps of: placing the semiconductor substrate comprising a polymer layer (24) deposited on the semiconductor substrate, a hard-mask (30) deposited on the polymer layer (24) and a photoresist mask (32) deposited on the hard-mask (30). The invention further, discloses performing a hard-mask opening step (34) comprising releasing a first fluoride gas (36) into the chamber. Furthermore, performing a polymer etching step (40) comprising releasing a second fluoride gas (42) into the chamber is disclosed. The invention also includes a hard-mask removal and tapered via step (46) to increase process margin.
摘要翻译：公开了用于产生尺寸精确的亚微米和微米通孔的改进的蚀刻工艺。具体地，本发明公开了一种沉积在半导体衬底（28）上的聚合物层（24）的通孔蚀刻工艺，包括以下步骤：将包含沉积在半导体衬底上的聚合物层（24）的半导体衬底放置在硬掩模（30），沉积在聚合物层（24）上的光致抗蚀剂掩模（32）和沉积在硬掩模（30）上的光致抗蚀剂掩模。本发明进一步公开了进行硬掩模打开步骤（34），包括将第一氟化物气体（36）释放到所述室中。此外，公开了包括将第二氟化物气体（42）释放到室中的聚合物蚀刻步骤（40）。本发明还包括硬掩模去除和锥形通过步骤（46）以增加工艺余量。

4. 发明申请

US20050181616A1 Dry etching process for compound semiconductors 有权
标题翻译：化学半导体的干蚀刻工艺
公开(公告)号：US20050181616A1
公开(公告)日：2005-08-18
申请号：US10782723
申请日：2004-02-18
申请人： Jennifer Wang , Huai-Min Sheng , Mike Barsky
发明人： Jennifer Wang , Huai-Min Sheng , Mike Barsky
IPC分类号： H01L21/306 , H01L21/302 , H01L21/461
CPC分类号： H01L21/30621
摘要： Accordingly, this invention relates to an dry etching process for semiconductor wafers. More particularly, the present invention discloses a dry etching process including a halogen etchant (24) and a nitrogen gas (28) that selectively etches a compound semiconductor material (18) faster than the front-side metal layers (16A)(16B). Further, the dry etching process produces a vertical wall profile on compound semiconductor material (18) in both X (38) and Y (40) crystalline directions without undercutting the top of a via-opening.
摘要翻译：因此，本发明涉及用于半导体晶片的干蚀刻工艺。更具体地，本发明公开了一种干蚀刻工艺，其包括选择性地比化学半导体材料（18）比前侧金属层（16A）（16B）蚀刻更多的卤素蚀刻剂（24）和氮气（28））。此外，干蚀刻工艺在X（38）和Y（40）结晶方向上在化合物半导体材料（18）上产生垂直壁轮廓，而不会削弱通孔开口的顶部。

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