专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US07957500B2 Fast phase-frequency detector arrangement 有权
标题翻译：快速相位检波器布置
公开(公告)号：US07957500B2
公开(公告)日：2011-06-07
申请号：US12759519
申请日：2010-04-13
申请人： Mihai Adrian Tiberiu Sanduleanu , Eduard Ferdinand Stikvoort
发明人： Mihai Adrian Tiberiu Sanduleanu , Eduard Ferdinand Stikvoort
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03L7/0896 , H03L7/0898
摘要： A detector arrangement for detecting a frequency error between an input signal (DATA) and a reference signal. The detector arrangement comprising first latch circuitry (L1, L2) for sampling a quadrature component (CKQ) of the reference signal based on the input signal, to generate a first binary signal (PDQ); second latch circuitry (L3, L4) for sampling an in-phase component (CKI) of the reference signal based on the input signal, to-generate a second binary signal (PD I); third latch circuitry (L5) for sampling the first binary signal based on the second binary signal, to generate the frequency error signal (FD). The detector further comprising control circuitry (TS) for selectively suppressing operation of a charge pump (82) to which the first binary signal (PDQ) is supplied, in response to a control signal derived from the second binary signal.
摘要翻译：一种用于检测输入信号（DATA）和参考信号之间的频率误差的检测器装置。检测器装置包括用于基于输入信号对参考信号的正交分量（CKQ）进行采样的第一锁存电路（L1，L2），以产生第一二进制信号（PDQ）; 用于基于所述输入信号对所述参考信号的同相分量（CKI）进行采样的第二锁存电路（L3，L4），以生成第二二进制信号（PD I）; 第三锁存电路（L5），用于基于第二二进制信号对第一二进制信号进行采样，以产生频率误差信号（FD）。检测器还包括用于响应于从第二二进制信号导出的控制信号，选择性地抑制提供第一二进制信号（PDQ）的电荷泵（82）的操作的控制电路（TS）。

2. 发明授权

US07768322B2 Low voltage, high-speed output-stage for laser or modulator driving 有权
标题翻译：用于激光或调制器驱动的低电压，高速输出级
公开(公告)号：US07768322B2
公开(公告)日：2010-08-03
申请号：US11577182
申请日：2005-09-30
申请人： Mihai Adrian Tiberiu Sanduleanu , Eduard F. Stikvoort
发明人： Mihai Adrian Tiberiu Sanduleanu , Eduard F. Stikvoort
IPC分类号： H03K3/00
CPC分类号： H03F1/02 , H03F3/217 , H03F3/30 , H03F3/45089 , H03F2203/45248 , H03F2203/45366 , H03K17/16
摘要： The present invention provides a driving circuit (100) in particular for driving a laser diode (700) or a modulator, at data speed in the order of Gb/s. The driving circuit (10) has a low-voltage, high-speed output stage capable of driving efficiently a laser diode (700) or a modulator The driver circuit (10) comprises a chain of circuits, said chain comprising a slew-rate control circuit, at least one translinear amplifier (200, 201, 202), a push/pull stage (300), and an output stage (400) for driving the load current. Due to its versatility, the driver can be used in other applications e.g. line drivers, cable drivers, high-speed serial interfaces for back-plane interconnect, etc. The driver can work at low supply voltages, e.g. 3.3V nominal down to 2.7V, with high power efficiency. One major clue is to use entirely the large signal current produced by the output stage, e.g. in the driven laser diode, without wasting current in supply lines.
摘要翻译：本发明提供一种驱动电路（100），特别是以Gb / s的数量速度驱动激光二极管（700）或调制器。驱动电路（10）具有能够有效驱动激光二极管（700）或调制器的低电压，高速输出级。驱动电路（10）包括电路链，所述链包括压摆率控制电路，至少一个跨线性放大器（200,201,202），推挽平台（300）和用于驱动负载电流的输出级（400）。由于其多功能性，驾驶员可以用于其他应用，例如线驱动器，电缆驱动器，用于背板互连的高速串行接口等。驱动器可以在低电源电压下工作，例如， 3.3V标称低至2.7V，具有高功率效率。一个主要线索是完全使用由输出级产生的大信号电流，例如，在驱动激光二极管中，不会浪费供电线路中的电流。

3. 发明授权

US07720188B2 Fast phase-frequency detector arrangement 有权
标题翻译：快速相位检波器布置
公开(公告)号：US07720188B2
公开(公告)日：2010-05-18
申请号：US10599326
申请日：2005-03-16
申请人： Mihai Adrian Tiberiu Sanduleanu , Eduard Ferdinand Stikvoort
发明人： Mihai Adrian Tiberiu Sanduleanu , Eduard Ferdinand Stikvoort
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03L7/0896 , H03L7/0898
摘要： The present invention relates to a detector arrangement and a charge pump circuit for a recovery circuit recovering timing information for random data. The detector arrangement comprises a first latch circuit for sampling a quadrature component of a reference signal based on an input signal, to generate a first binary signal, a second latch circuit for sampling an in-phase component of the reference signal based on the input signal, to generate a second binary signal, and a third latch circuit for sampling the first binary signal based on the second binary signal, to generate a frequency error signal. Furthermore, the charge pump circuit comprises a differential input circuit and a control circuit for controlling a tail current of the differential input circuit in response to a frequency-locked state of frequency detector arrangement.
摘要翻译：本发明涉及用于恢复随机数据的定时信息的恢复电路的检测器装置和电荷泵电路。检测器装置包括第一锁存电路，用于基于输入信号对参考信号的正交分量进行采样，以产生第一二进制信号;第二锁存电路，用于基于输入信号对参考信号的同相分量进行采样以产生第二二进制信号，以及第三锁存电路，用于基于第二二进制信号对第一二进制信号进行采样，以产生频率误差信号。此外，电荷泵电路包括差分输入电路和用于响应于频率检测器装置的频率锁定状态来控制差分输入电路的尾部电流的控制电路。

4. 发明授权

US07466785B2 PLL with balanced quadricorrelator 有权
标题翻译： PLL与平衡二次相关器
公开(公告)号：US07466785B2
公开(公告)日：2008-12-16
申请号：US10533507
申请日：2003-10-08
申请人： Mihai Adrian Tiberiu Sanduleanu , Dominicus Martinus Wilhelmus Leenaerts
发明人： Mihai Adrian Tiberiu Sanduleanu , Dominicus Martinus Wilhelmus Leenaerts
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03L7/0891 , H03L7/091 , H03L2207/06 , H04L7/0274
摘要： A Phase Locked Loop (1) comprising a frequency detector (10) including a balanced quadricorrelator (2), the loop (1) being characterized in that the quadricorrelator (2) comprises double edge clocked bi-stable circuits (21, 22, 23, 24, 25, 26, 27, 28) coupled to multiplexers (31, 32, 33, 34) being controlled by a signal having the same bitrate as the incoming D signal (D).
摘要翻译：一种锁相环（1），包括包括平衡四极管相关器（2）的频率检测器（10），所述环路（1）的特征在于所述四极管相关器（2）包括双边沿时钟双稳态电路（21,22,23 ，24,25,26,27,28）由耦合到多路复用器（31,32,33,34）的信号由与输入D信号（D）具有相同比特率的信号控制。

5. 发明授权

US07285999B2 Circuit for use in frequency or phase detector 有权
标题翻译：用于频率或相位检测器的电路
公开(公告)号：US07285999B2
公开(公告)日：2007-10-23
申请号：US10550345
申请日：2004-03-22
申请人： Mihai Adrian Tiberiu Sanduleanu , Eduard Ferdinand Stikvoort
发明人： Mihai Adrian Tiberiu Sanduleanu , Eduard Ferdinand Stikvoort
IPC分类号： G11C27/02
CPC分类号： G11C27/024 , G01R25/005 , H03L7/085 , H03L7/087 , H04L7/033
摘要： A tracking data cell (10) comprising:—a pair of track and hold circuits (1, 1′) coupled to a first multiplexer (5),—a clock signal (H+, H−) being inputted substantially in anti-phase in the respective track and hold circuits (1, 1′) for determining a receipt of a data signal (D+, D−) having a rate, —said track and hold circuits (1, 1′) providing an output signal (O) having a substantially half rate.
摘要翻译：一种跟踪数据单元（10），包括： - 耦合到第一多路复用器（5）的一对跟踪和保持电路（1,1'）， - 时钟信号（H +，H-）基本上被反相输入用于确定具有速率的数据信号（D +，D-）的接收的相应的跟踪和保持电路（1,1'），提供输出信号（1），提供输出信号（1）大概是一半的。

6. 发明授权

US07251573B2 Phase detector 有权
标题翻译：相位检测器
公开(公告)号：US07251573B2
公开(公告)日：2007-07-31
申请号：US10569125
申请日：2004-08-11
申请人： Mihai Adrian Tiberiu Sanduleanu , Eduard Ferdinand Stikvoort
发明人： Mihai Adrian Tiberiu Sanduleanu , Eduard Ferdinand Stikvoort
IPC分类号： G06F19/00
CPC分类号： H03D13/003 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/107 , H04L7/033
摘要： The present invention concerns a phase Detector for detecting a phase difference between a data clock DATA-CLK and a reference clock REF-CLK using a data signal DATA. A trasnsition of the data signal DATA is synchronous with a transition of the data clock DATA-CLK. The data clock DATA-CLK and the reference clock REF-CLK have the same frequency. The phase detector includes first signal generator for generating a first binary signal ERRQ a second signal generator for generating a second binary signal ERRI. The pulse width of the second binary signal ERRI is equal to a second time difference ΔT2 between a transition of the data signal DATA and a transition of the second reference clock signal CKI adjacent to the transition of the data signal DATA.
摘要翻译：本发明涉及一种用于使用数据信号DATA检测数据时钟DATA-CLK和参考时钟REF-CLK之间的相位差的相位检测器。数据信号DATA的跟踪与数据时钟DATA-CLK的转换同步。数据时钟DATA-CLK和参考时钟REF-CLK具有相同的频率。相位检测器包括用于产生第一二进制信号ERRQ的第一信号发生器，用于产生第二二进制信号ERRI的第二信号发生器。第二二进制信号ERRI的脉冲宽度等于数据信号DATA的转变与与数据信号DATA的转变相邻的第二参考时钟信号CKI的转变之间的第二时间差ΔT2。

7. 发明申请

US20120188109A1 Track and Hold Amplifiers and Digital Calibration for Analog-to-Digital Converters 有权
标题翻译：跟踪和保持放大器和模数转换器的数字校准
公开(公告)号：US20120188109A1
公开(公告)日：2012-07-26
申请号：US13010285
申请日：2011-01-20
申请人： Mihai Adrian TIberiu Sanduleanu , Jean-Olivier Plouchart , Zeynep Toprak Deniz
发明人： Mihai Adrian TIberiu Sanduleanu , Jean-Olivier Plouchart , Zeynep Toprak Deniz
IPC分类号： H03M1/10 , G11C27/02
CPC分类号： G11C27/02 , H03M1/1061 , H03M1/365
摘要： An exemplary differential track and hold amplifier includes a track stage including first and second linearized pairs connected in series at their respective inputs and in parallel at their respective outputs. The differential track and hold amplifier also includes a hold stage selectively coupled to the outputs of the first and second linearized pairs. The hold stage includes a unity gain buffer with feedback having a hold capacitor interconnected across its outputs. The differential track and hold amplifier also includes an output buffer coupled to the outputs of the hold stage. An exemplary analog-to-digital converter includes a differential track-and-hold amplifier, a voltage ladder, and a plurality of slices. Each of the slices in turn includes a differential preamplifier coupled to the track-and-hold amplifier and to a corresponding location on the voltage ladder; a current mode logic latch comparator coupled to the differential preamplifier; a large-swing latch coupled to the current mode logic latch comparator; a complementary metal oxide semiconductor latch having a dummy load; a calibration digital to analog converter connected across outputs of the differential preamplifier to inject calibration currents; and a register coupled to the calibration digital to analog converter and storing calibration values for use thereby. The analog-to-digital converter also includes a multiplexer which multiplexes outputs of the complementary metal oxide semiconductor latches down to a predetermined number of outputs.
摘要翻译：示例性的差分跟踪和保持放大器包括轨道平台，该轨道平台包括在其各自的输入处并联并联的第一和第二线性化对，并且在它们各自的输出处并联。差分跟踪和保持放大器还包括选择性地耦合到第一和第二线性化对的输出的保持级。保持级包括具有反馈的单位增益缓冲器，其具有在其输出端互连的保持电容器。差分跟踪和保持放大器还包括耦合到保持级的输出的输出缓冲器。示例性模数转换器包括差分跟踪保持放大器，电压梯和多个片。每个切片依次包括耦合到跟踪保持放大器和电压梯上相应位置的差分前置放大器; 耦合到差分前置放大器的电流模式逻辑锁存比较器; 耦合到电流模式逻辑锁存比较器的大摆动锁存器; 具有虚拟负载的互补金属氧化物半导体锁存器; 连接在差分前置放大器的输出端的校准数模转换器，以注入校准电流; 以及耦合到校准数模转换器的寄存器，并存储用于其的校准值。模数转换器还包括多路复用器，其将互补金属氧化物半导体锁存器的输出多路复用到预定数量的输出。

8. 发明授权

US07821342B2 Device comprising a feedback-less gain controlled amplifier 有权
标题翻译：装置包括无反馈增益控制放大器
公开(公告)号：US07821342B2
公开(公告)日：2010-10-26
申请号：US11994783
申请日：2006-07-03
申请人： Mihai Adrian Tiberiu Sanduleanu , Eduard F. Stikvoort
发明人： Mihai Adrian Tiberiu Sanduleanu , Eduard F. Stikvoort
IPC分类号： H03F3/04
CPC分类号： H03F3/45 , H03F2200/372
摘要： Devices (1,2) comprising feedback-less amplifiers (16,19,26,29) that are gain controlled introduce linear relationships between output signals and input signals of the feedback-less amplifiers (16,19,26,29) by providing the feedback-less amplifiers (16,19,26,29) sub-circuits in the form of first transistors (33) operated in their triode regions for receiving input signals and second sub-circuits in the form of second transistors (34) for receiving control signals and third sub-circuits in the form of resistors (35) for generating output signals, whereby the respective first and second and third sub-circuits form a serial path. Second circuits (4) receive gain signals and convert the gain signals into the control signals. The control signals are copies of the gain signals. The second circuits (4) comprise current sources (6) and third and fourth transistors (41,42). The current sources (6) comprise fifth and sixth transistors (61,62). The second circuits (4) further comprise voltage sources (9) further current sources. Third circuits (8) compensate common mode currents.
摘要翻译：包括无增益控制放大器（16,19,26,29）的设备（1,2），其被增益控制通过提供无反馈放大器（16,19,26,29）的输出信号和输入信号之间的线性关系来引入在第三晶体管（33）的形式的无反馈放大器（16,19,26,29）子电路在其三极管区域中工作以接收输入信号，第二晶体管（34）形式的第二子电路用于以电阻器（35）的形式接收控制信号和第三子电路，用于产生输出信号，由此相应的第一和第二和第三子电路形成串行路径。第二电路（4）接收增益信号并将增益信号转换成控制信号。控制信号是增益信号的副本。第二电路（4）包括电流源（6）和第三和第四晶体管（41,42）。电流源（6）包括第五和第六晶体管（61,62）。第二电路（4）还包括电压源（9）的另外的电流源。第三回路（8）补偿共模电流。

9. 发明授权

US07804926B2 PLL using unbalanced quadricorrelator 失效
标题翻译： PLL使用不平衡二次相关器
公开(公告)号：US07804926B2
公开(公告)日：2010-09-28
申请号：US10533058
申请日：2003-10-08
申请人： Mihai Adrian Tiberiu Sanduleanu
发明人： Mihai Adrian Tiberiu Sanduleanu
IPC分类号： H03D3/24
CPC分类号： H03L7/087 , H03D13/003 , H03L7/091 , H03L2207/06 , H04L7/0274
摘要： A Phase Locked Loop (1) used in a data and clock recovery comprising a frequency detector (10) including a quadricorrelator (2), the quadricorrelator (2) comprising a frequency detector including double edge clocked bi-stable circuits (21, 22, 23, 24) coupled to a first multiplexer (31) and to a second multiplexer (32) being controlled by a signal having a same bitrate as the incoming signal (D), and a phase detector (DFF) controlled by a first signal pair (PQ, PQ provided by the first multiplexer (31) and by a second signal pair (PI, PI) provided by the second multiplexer (32).
摘要翻译：一种用于数据和时钟恢复的锁相环（1），包括包括二次相关器（2）的频率检测器（10），所述四相关器（2）包括频率检测器，所述频率检测器包括双边沿时钟双稳态电路（21,22，耦合到第一多路复用器（31）的第二多路复用器（32）和由具有与输入信号（D）相同的比特率的信号控制的第二多路复用器（32），以及由第一信号对（D）控制的相位检测器（PQ，PQ由第一多路复用器31提供）和由第二多路复用器（32）提供的第二信号对（PI，PI）。

10. 发明授权

US06781475B2 Transmission lines arrangement 有权
标题翻译：传输线布置
公开(公告)号：US06781475B2
公开(公告)日：2004-08-24
申请号：US10198494
申请日：2002-07-18
申请人： Hugo Veenstra , Edwin Van Der Heijden , Mihai Adrian Tiberiu Sanduleanu
发明人： Hugo Veenstra , Edwin Van Der Heijden , Mihai Adrian Tiberiu Sanduleanu
IPC分类号： H01P110
CPC分类号： H04Q3/521 , H04Q2213/1302 , H04Q2213/1304 , H04Q2213/13305 , H04Q2213/13306
摘要： A transmission lines arrangement comprising a first plurality of transmission lines each transmission line having an effective characteristic impedance. The arrangement further comprises a second plurality of transmission lines, said first plurality of transmission lines being coupled to a plurality of switching elements. The plurality of switching elements are conceived to redirect an input signal from one transmission line of the first plurality of transmission lines to at least one transmission line of the second plurality of transmission lines. The arrangement is characterized in that each of the switching elements of the plurality of switching elements have a relatively high input impedance in comparison with the effective characteristic impedance and a relatively high output impedance in comparison with the effective characteristic impedance. Furthermore, each transmission line of the first plurality of transmission lines is further coupled to an impedance that is substantially equal to the effective characteristic impedance of said transmission line.
摘要翻译：一种传输线布置，包括第一多个传输线，每个传输线具有有效的特征阻抗。该布置还包括第二多个传输线，所述第一多个传输线耦合到多个开关元件。多个开关元件被设想为将来自第一多个传输线的一个传输线的输入信号重定向到第二多个传输线的至少一个传输线。该装置的特征在于，与有效特性阻抗相比，多个开关元件的每个开关元件与有效特性阻抗相比具有相对较高的输入阻抗和相对较高的输出阻抗。此外，第一多个传输线的每个传输线还进一步耦合到基本上等于所述传输线的有效特性阻抗的阻抗。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式