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1. 发明授权

US07793089B2 Configurable backplane connectivity for an electrical device 有权
标题翻译：电气设备的可配置背板连接
公开(公告)号：US07793089B2
公开(公告)日：2010-09-07
申请号：US11669839
申请日：2007-01-31
申请人： Kevin B. Leigh , Michael L. Sabotta , Albert H. Chang
发明人： Kevin B. Leigh , Michael L. Sabotta , Albert H. Chang
IPC分类号： G06F3/00 , G06F9/00 , G06F13/00 , G06F13/20 , G06F15/177 , H05K7/10
CPC分类号： G06F13/409 , G06F13/4022
摘要： A method comprises obtaining connectivity information from a plurality of electrical devices. Each such electrical device is separately coupled to a backplane, and at least one electrical device comprises a plurality of electrical interfaces adapted to be selectively coupled to each of multiple other electrical devices. Based on connectivity information from the at least one electrical device, the method further comprises providing configuration information to the at least one electrical device to cause the at least one electrical device to electrically couple to a target other electrical device via the backplane.
摘要翻译：一种方法包括从多个电气设备获得连接信息。每个这样的电气设备单独耦合到背板，并且至少一个电气设备包括适于选择性地耦合到多个其他电气设备中的每一个的多个电接口。基于来自至少一个电气设备的连接信息，所述方法还包括向所述至少一个电气设备提供配置信息以使所述至少一个电气设备经由所述背板电耦合到目标其他电气设备。

2. 发明授权

US6154789A Peripheral controller comprising first messaging unit for communication with first OS driver and second messaging unit for communication with second OS driver for mass-storage peripheral 失效
标题翻译：外围控制器包括用于与第一OS驱动器通信的第一消息单元和用于与用于大容量存储外设的第二OS驱动器通信的第二消息单元
公开(公告)号：US6154789A
公开(公告)日：2000-11-28
申请号：US97409
申请日：1998-06-15
申请人： Thomas W. Grieff , Bryan A. Jones , Michael L. Sabotta
发明人： Thomas W. Grieff , Bryan A. Jones , Michael L. Sabotta
IPC分类号： G06F13/10 , G06F13/38 , G06F3/00 , G06F13/12
CPC分类号： G06F13/385 , G06F13/102
摘要： An embodiment of the present invention provides a peripheral controller for coupling a mass storage peripheral to a computer system. In a disclosed embodiment the peripheral controller is a disk array controller programmed for RAID. The peripheral controller includes a first messaging unit (FMU), a second messaging unit (SMU), and a peripheral interface which are connected by a local bus. The FMU responds to messages from a first operating system driver. The SMU responds to messages from a different second operating system driver. In one embodiment, the FMU responds to commands from the first operating system driver which is non-standard. In another embodiment, the SMU responds to commands from the second operating system driver which is compatible with the I2O standard. In the disclosed embodiment, the peripheral interface controls mass storage peripherals in response to messages sent to the FMU or the SMU.
摘要翻译：本发明的实施例提供了一种用于将大容量存储外围设备耦合到计算机系统的外围控制器。在公开的实施例中，外围控制器是针对RAID编程的盘阵列控制器。外围控制器包括通过本地总线连接的第一消息接发单元（FMU），第二通信单元（SMU）和外围接口。 FMU响应来自第一个操作系统驱动程序的消息。 SMU响应来自不同第二操作系统驱动程序的消息。在一个实施例中，FMU响应来自非标准的第一操作系统驱动器的命令。在另一实施例中，SMU响应来自与I2O标准兼容的第二操作系统驱动器的命令。在所公开的实施例中，外围接口响应于发送到FMU或SMU的消息来控制大容量存储外设。

3. 发明授权

US07149825B2 System and method for sending data at sampling rate based on bit transfer period 失效
标题翻译：基于位传输周期以采样率发送数据的系统和方法
公开(公告)号：US07149825B2
公开(公告)日：2006-12-12
申请号：US10637286
申请日：2003-08-08
申请人： Michael S. Bunker , Michael L. Sabotta , Michael D. White , Sajid A. Momin
发明人： Michael S. Bunker , Michael L. Sabotta , Michael D. White , Sajid A. Momin
IPC分类号： G06F3/00 , G06F13/00
CPC分类号： G06F13/387 , H04L7/0008
摘要： A method and apparatus for sending data. One exemplary embodiment may be a method comprising sending a data rate synchronization pulse from drive controller in a computer system to a storage device controller, calculating a bit transfer period by the storage device controller based on the time duration of the data rate synchronization pulse, serially driving a plurality of bits from the drive controller at a rate based on the bit transfer period, and sampling at the rate based on the bit transfer period to receive the plurality of bits by the storage device controller.
摘要翻译：一种用于发送数据的方法和装置。一个示例性实施例可以是一种方法，包括从计算机系统中的驱动控制器向存储设备控制器发送数据速率同步脉冲，基于数据速率同步脉冲的持续时间，由存储设备控制器计算位传输周期以驱动控制器为基础，以比特传输周期的速率驱动多个比特，并根据比特传送周期以该速率进行采样，由存储装置控制器接收多个比特。

4. 发明授权

US07007184B2 DIMM connector accomodating sideband signals for battery status and/or control 有权
标题翻译： DIMM连接器，用于容纳用于电池状态和/或控制的边带信号
公开(公告)号：US07007184B2
公开(公告)日：2006-02-28
申请号：US09948890
申请日：2001-09-07
申请人： Michael L. Sabotta , M. Scott Bunker
发明人： Michael L. Sabotta , M. Scott Bunker
IPC分类号： H01M10/46
CPC分类号： G11C5/141 , G06F13/4022 , G11C5/14
摘要： A DIMM connector, including pins for transmitting side band signals for at least one of battery status or control for a battery backed cache is disclosed.
摘要翻译：公开了一种DIMM连接器，其包括用于发送用于电池状态或电池保护的高速缓存的控制中的至少一个的边带信号的引脚。

5. 发明授权

US5986880A Electronic apparatus having I/O board with cable-free redundant adapter cards thereon 失效
标题翻译：具有I / O板的电子设备，其上具有无电缆冗余适配器卡
公开(公告)号：US5986880A
公开(公告)日：1999-11-16
申请号：US876730
申请日：1997-06-16
申请人： Paul A. Santeler , Reza M. Bacchus , Michael L. Sabotta
发明人： Paul A. Santeler , Reza M. Bacchus , Michael L. Sabotta
IPC分类号： G06F1/18 , G06F13/40 , G06F1/16 , H05K7/10
CPC分类号： G06F13/409
摘要： The cage-supported hard disk drives in a computer server system are coupled to connectors on the cage back plane circuit boards and are controlled by a pair of array controller cards which are hot-plug connected in a redundant manner on the system I/O board using a pair of connectors mounted on the I/O board, each connector having first and second sets of electrical contacts thereon. Connector edge portions of the array controller cards are plugged into the I/O board connectors and have first and second sets of electrical contacts that engage the corresponding first and second sets of electrical contacts on their associated I/O board connectors. Formed on the I/O board are (1) a peripheral interconnect bus structure connected to the first sets of connector electrical contacts, (2) an electrical bus structure connected to the second sets of connector electrical contacts and associated cable connectors, and (3) an intercontroller bus structure connected between the second sets of connector electrical contacts and enabling the two array controller cards to communicate with one another independently of the peripheral interconnect bus structure. Electrical cables are interconnected between the electrical bus structure and the back plane circuit boards to couple the array controller cards thereto in a redundant control manner without requiring direct cable connection to either of the array controller cards.
摘要翻译：计算机服务器系统中的笼式硬盘驱动器耦合到保持架背板电路板上的连接器，并由一对阵列控制器卡控制，这些阵列控制器卡以冗余方式热插拔连接到系统I / O板上使用安装在I / O板上的一对连接器，每个连接器在其上具有第一组和第二组电触点。阵列控制器卡的连接器边缘部分插入到I / O板连接器中，并且具有接合在其相关联的I / O板连接器上的对应的第一和第二组电触头的第一组和第二组电触点。在I / O板上形成有（1）连接到第一组连接器电触点的外围互连总线结构，（2）连接到第二组连接器电触头和相关电缆连接器的电总线结构，和（3 ）连接在所述第二组连接器电触头之间并且使得所述两个阵列控制器卡能够独立于所述外围互连总线结构彼此通信的互连控制器总线结构。电气电缆在电气总线结构和背板电路板之间互连，以便以冗余控制方式将阵列控制器卡耦合到其上，而不需要直接连接到阵列控制器卡中的任何一个。

6. 发明授权

US5848251A Secondary channel for command information for fibre channel system interface bus 失效
标题翻译：光纤通道系统接口总线命令信息的二级通道
公开(公告)号：US5848251A
公开(公告)日：1998-12-08
申请号：US692516
申请日：1996-08-06
申请人： Lawrence W. Lomelino , Thomas W. Grieff , Michael L. Sabotta
发明人： Lawrence W. Lomelino , Thomas W. Grieff , Michael L. Sabotta
IPC分类号： G06F13/12 , G06F13/42 , G06F13/14
CPC分类号： G06F13/4278
摘要： The present invention relates to a secondary channel for a point-to-point burst style bus associated with a computer system. The point-to-point bus may originate as a standardized bus from a fibre channel controller. The point-to-point bus connects to another circuit which may be a bridge circuit, a minicomputer or a peripheral device. A secondary channel is also connected to the point-to-point bus and is adapted to share the bus by receiving information having predetermined addresses. The information recieved by the secondary channel can be stored in a memory that is shared with a processor. Command/control information can be extracted from the point-to-point bus before data is transferred through the bridge circuit in order to allow the data to be acted on more quickly by processing/storage devices since the control data was already made available to the storage devices via the secondary channel.
摘要翻译：本发明涉及一种与计算机系统相关联的点对点突发样式总线的辅助信道。点对点总线可以作为来自光纤通道控制器的标准化总线发起。点对点总线连接到另一个可能是桥接电路，小型计算机或外围设备的电路。辅助信道也连接到点对点总线，并且适于通过接收具有预定地址的信息来共享总线。辅助频道接收到的信息可以存储在与处理器共享的存储器中。在通过桥接电路传输数据之前，可以从点对点总线提取命令/控制信息，以便通过处理/存储设备更快速地执行数据，因为控制数据已经可用于存储设备通过辅助通道。

7. 发明授权

US10123464B2 Heat dissipating system 有权
公开(公告)号：US10123464B2
公开(公告)日：2018-11-06
申请号：US14376124
申请日：2012-02-09
申请人： David A Moore , John P Franz , Tahir Cader , Michael L Sabotta
发明人： David A Moore , John P Franz , Tahir Cader , Michael L Sabotta
IPC分类号： H05K7/20 , G06F1/20 , H02G5/10
摘要： Heat dissipating system and method are disclosed. An example method includes removing heat from a rack component via a thermal transport. The method also includes applying a pressure at a fluid cooled thermal bus bar on a rack system to form a thermally conductive dry disconnect interface and form a heat path between the thermal transport and the fluid cooled thermal bus bar.

8. 发明申请

US20140376176A1 LIQUID TEMPERATURE CONTROL COOLING 有权
标题翻译：液体温度控制冷却
公开(公告)号：US20140376176A1
公开(公告)日：2014-12-25
申请号：US14376138
申请日：2012-03-12
申请人： John P. Franz , Michael L. Sabotta , Tahir Cader , David A. Moore
发明人： John P. Franz , Michael L. Sabotta , Tahir Cader , David A. Moore
IPC分类号： G06F1/20
CPC分类号： G06F1/20 , F28D15/0275 , G06F1/206 , H05K7/20772 , H05K7/20781
摘要： Examples of the present disclosure may include methods and systems for liquid temperature control cooling. An example of a liquid temperature control cooling system for an electronics rack (100, 200a, 200b) can include a number of electronic devices (102, 202) in the electronics rack (100, 200a, 200b), a panel (108-1, 108-2, 208-1, 224-1, 224-2) that extends from a roof (226) to a floor (228) inside the electronics rack (100, 200a, 200b), where a face of the panel (108-1, 108-2, 208-1, 224-1, 224-2) is parallel to a direction in which the number of electronic devices (100, 200a, 200b) slide into the electronics rack (100, 200a, 200b) and perpendicular to a front of the electronics rack, and a heat receiving structure (112, 212, 312, 412) that is integrated into the panel (108-1, 108-2, 208-1, 224-1, 224-2) and that is thermally coupled to the number of electronic devices (102, 202) through the panel (108-1, 108-2, 208-1, 224-1, 224-2), where the heat receiving structure (112, 212, 312, 412) can include a liquid flow compartment (330, 442) an input (216, 316, 416) to receive cool liquid into the liquid flow compartment (330, 442), and a control valve (214, 314, 414-1, 414-2, 414-3, 414-4) to release warm liquid from the liquid flow compartment (330, 442).
摘要翻译：本公开的实例可以包括用于液体温度控制冷却的方法和系统。用于电子机架（100,200a，200b）的液体温度控制冷却系统的示例可以包括电子机架（100,200a，200b）中的多个电子设备（102,202），面板（108-1 ，108-2,208-1,224-1,224-2），其从所述电子机架（100,200a，200b）内部的屋顶（226）延伸到地板（228），其中所述面板 108-1,108-2,208-1,224-1,224-2）平行于电子设备（100,200a，200b）的数量滑入电子机架（100,200a，200b）的方向）和垂直于所述电子机架的前部的热接收结构（112,212,312,412），其被集成到所述面板（108-1,108-2,208-1,224-1,224-212）中， 2），并且其通过面板（108-1,108-2,208-1,224-1,224-2）与电子设备（102,202）的数量热耦合，其中热接收结构（112），212,312,412）可以包括液体流动隔室（330,442），输入端（216,316,416）以将冷却液体接收到液体流动室（330,442）和用于从液体流动室（330,442）释放温热液体的控制阀（214,314,414-1,414-2,414-3,414-4）。

9. 发明授权

US08526177B2 Fan for cooling multiple processors housed in a sub-chassis 有权
标题翻译：用于冷却容纳在子机箱中的多个处理器的风扇
公开(公告)号：US08526177B2
公开(公告)日：2013-09-03
申请号：US12773629
申请日：2010-05-04
申请人： David M. Paquin , John D. Nguyen , Michael L. Sabotta , Larry E. Wilson
发明人： David M. Paquin , John D. Nguyen , Michael L. Sabotta , Larry E. Wilson
IPC分类号： H05K7/20 , H05K5/00
CPC分类号： G06F1/20 , H05K7/20727
摘要： A chassis comprises a printed circuit board (PCB) and a sub-chassis housing multiple processors that couple to the PCB. The sub-chassis is disposed above and parallel to the PCB. The multiple processors are cooled by a fan disposed on the sub-chassis.
摘要翻译：底盘包括印刷电路板（PCB）和底架，其容纳耦合到PCB的多个处理器。副底盘设置在PCB的上方并与PCB平行。多个处理器由设置在子机架上的风扇冷却。

10. 发明授权

US6061752A Technique for hot plugging a peripheral controller card containing PCI and SCSI buses on a single connector into a host system board 失效
标题翻译：将单个连接器上包含PCI和SCSI总线的外围控制器卡插入主机系统板的技术
公开(公告)号：US6061752A
公开(公告)日：2000-05-09
申请号：US97493
申请日：1998-06-15
申请人： Bryan A. Jones , Michael L. Sabotta , Thomas W. Grieff
发明人： Bryan A. Jones , Michael L. Sabotta , Thomas W. Grieff
IPC分类号： G06F1/18 , G06F13/40 , G06F13/00
CPC分类号： G06F13/409
摘要： An embodiment of the present invention discloses a technique that allows hot plugging a peripheral controller card, containing both a local bus and a peripheral bus on a single connector, into a host system board containing a host system bus and a host I/O bus. When mating the peripheral controller card to the host system board a local device power supply (LDPS) is inactive, a peripheral device power bus (PDPB) is powered, and signal lines of a peripheral device are maintained in a high impedance state. Following a delay after the mating, the LDPS is activated by the host operating system (OS). Following the activation of the LDPS, the host system bus is coupled to the single connector through switches that are under OS control. In response to the activation of the LDPS, the signal lines of the peripheral device are enabled.In a disclosed embodiment the peripheral controller card is a disk array controller card, the local bus is a PCI bus, and the peripheral bus is a SCSI bus. In one embodiment the disk array controller card is coupled to a mass storage peripheral and in another embodiment is programmed for RAID. An advantage of an embodiment of the present invention is that a PCI bus and a SCSI bus are carried on a single peripheral connector which provides cable management and readily allows hot plugging a redundant peripheral controller card into the host system board.
摘要翻译：本发明的实施例公开了一种技术，其允许将包含本地总线和外围总线的外围控制器卡热插拔到单个连接器上，并将其插入到包含主机系统总线和主机I / O总线的主机系统板中。外围设备电源总线（PDPB）为外部设备电源总线（PDPB）供电时，外围设备的信号线保持在高阻抗状态。在配对后延时，LDPS由主机操作系统（OS）激活。在激活LDPS之后，主机系统总线通过处于OS控制下的开关耦合到单个连接器。响应于LDPS的激活，外围设备的信号线被使能。在公开的实施例中，外围控制器卡是磁盘阵列控制卡，局部总线是PCI总线，外围总线是SCSI总线。在一个实施例中，磁盘阵列控制器卡耦合到大容量存储外围设备，并且在另一个实施例中被编程用于RAID。本发明的一个实施例的优点在于，PCI总线和SCSI总线被承载在提供电缆管理的单个外围连接器上，并且容易地将冗余外围控制器卡热插拔到主机系统板中。

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