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    • 1. 发明授权
    • Quiet fan speed control
    • 安静的风扇转速控制
    • US07541698B2
    • 2009-06-02
    • US11824639
    • 2007-07-02
    • Michael J. Dhuey
    • Michael J. Dhuey
    • H01H35/00
    • H05K7/20209F04D27/004G06F1/206Y10T307/858
    • A novel circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment the limiter includes a switch for combining a PWM signal with a DC voltage at an output.
    • 用于驱动风扇的新颖电路包括用于向风扇供应驱动电力的输出端子,脉宽调制驱动器和限幅器。 风扇的第一电源端子保持在第一电压(例如0V),并且风扇的第二电源端子耦合到驱动器电路的输出端子。 PWM驱动器在输出端子上提供一系列风扇驱动脉冲,并且限幅器防止输出端子上的电压下降到预定电压以下。 预定电压大于风扇第一电源端子保持的第一电压,并且即使当PWM信号的占空比为0%时也足以使风扇保持运动。 在特定实施例中,限幅器包括电压钳。 在更具体的实施例中,电压钳是二极管。 在另一特定实施例中,限幅器包括用于在输出处将PWM信号与DC电压组合的开关。
    • 2. 发明授权
    • Quiet fan speed control
    • 安静的风扇转速控制
    • US06924568B2
    • 2005-08-02
    • US10214414
    • 2002-08-06
    • Michael J. Dhuey
    • Michael J. Dhuey
    • G06F1/20H05K7/20H01H35/00
    • H05K7/20209F04D27/004G06F1/206Y10T307/858
    • A novel a circuit for driving a fan includes an output terminal for supplying the fan with drive power, a pulse width modulation driver, and a limiter. A first power terminal of the fan is held at a first voltage (e.g., 0V), and a second power terminal of the fan is coupled to the output terminal of the driver circuit. The PWM driver provides a series of fan drive pulses on the output terminal, and the limiter prevents the voltage on the output terminal from falling below a predetermined voltage. The predetermined voltage is greater than the first voltage at which the fan's first power terminal is held, and is sufficient to keep the fan in motion even when the duty cycle of the PWM signal is 0%. In a particular embodiment the limiter includes a voltage clamp. In a more particular embodiment, the voltage clamp is a diode. In another particular embodiment, the limiter includes a switch for combining a PWM signal with a DC voltage at an output.
    • 用于驱动风扇的新型电路包括用于向风扇供应驱动电力的输出端子,脉宽调制驱动器和限幅器。 风扇的第一电源端子保持在第一电压(例如0V),并且风扇的第二电源端子耦合到驱动器电路的输出端子。 PWM驱动器在输出端子上提供一系列风扇驱动脉冲,并且限幅器防止输出端子上的电压下降到预定电压以下。 预定电压大于风扇第一电源端子保持的第一电压,并且即使当PWM信号的占空比为0%时也足以使风扇保持运动。 在特定实施例中,限幅器包括电压钳。 在更具体的实施例中,电压钳是二极管。 在另一特定实施例中,限幅器包括一个开关,用于将PWM信号与输出端的直流电压进行组合。
    • 4. 发明授权
    • Methods and apparatus for controlling back-to-back burst reads in a
cache system
    • 用于控制高速缓存系统中的背对背突发读取的方法和装置
    • US5603007A
    • 1997-02-11
    • US212081
    • 1994-03-14
    • Farid A. YazdyMichael J. Dhuey
    • Farid A. YazdyMichael J. Dhuey
    • G06F12/08
    • G06F12/0879
    • Circuit arrangements and methods are disclosed for upgrading an 040-based personal computer system using an optional, peripheral add-in card. In one embodiment, the present invention comprises a PowerPC-based microprocessor, such as the MPC601, having one megabyte of on-board direct mapped level 2 external cache memory arranged as tag and data blocks. The PowerPC-based board is inserted into a processor-direct data path sharing the data and address bus with the 040 microprocessor. System random access memory (RAM), I/O, and other functional blocks are present on the main board comprising the 040-based computer. The MPC601 is coupled via address and data buses to the tag cache, a bus translation unit (BTU), a read only memory (ROM) storing the operating system code for the PowerPC microprocessor, the data cache, a dual frequency clock buffer, and other interface components such as a processor-direct data path including address and data latches. When the computer is turned on, the BTU coupled to the data bus sequentially clears all valid bits in the tag cache, whereafter the cache and memory map are enabled. The 040 processor on the main board is disabled after power-up by using the 040 JTAG test port after inactivating the power-on fast reset. By shifting in appropriate RESET, TCK, and TMS patterns, the 040 will be placed in a nonfunctional, high impedance state. However, DRAM present on the motherboard may be accessed by the 601 after a cache miss. DRAM is accessed via a 601-040 transaction translation operation within the BTU, wherein coded tables map the MPC601 transaction into the appropriate 040 transaction.
    • 公开了用于使用可选的外围附加卡升级基于040的个人计算机系统的电路布置和方法。 在一个实施例中,本发明包括基于PowerPC的微处理器,诸如MPC601,其具有布置为标签和数据块的一兆字节的车载直接映射级2外部高速缓冲存储器。 基于PowerPC的电路板插入与040微处理器共享数据和地址总线的处理器直接数据通路。 系统随机存取存储器(RAM),I / O和其他功能块存在于包含基于040的计算机的主板上。 MPC601通过地址和数据总线耦合到标签缓存,总线转换单元(BTU),存储用于PowerPC微处理器的操作系统代码的只读存储器(ROM),数据高速缓存,双频时钟缓冲器和 其他接口组件,例如包括地址和数据锁存器的处理器直接数据路径。 当计算机打开时,耦合到数据总线的BTU顺序地清除标签高速缓存中的所有有效位,之后启用高速缓存和存储器映射。 上电后,主板上的040处理器在禁用上电快速复位后使用040 JTAG测试端口禁用。 通过在适当的RESET,TCK和TMS模式下移位,040将处于非功能,高阻抗状态。 然而,存在于主板上的DRAM可能在高速缓存未命中之后由601访问。 通过BTU内的601-040事务翻译操作访问DRAM,其中编码表将MPC601事务映射到适当的040事务。