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1. 发明授权

US08832616B2 Voltage drop effect on static timing analysis for multi-phase sequential circuit 有权
标题翻译：对多相顺序电路静态时序分析的电压降影响
公开(公告)号：US08832616B2
公开(公告)日：2014-09-09
申请号：US13414052
申请日：2012-03-07
申请人： Mau-chung Chang
发明人： Mau-chung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5036 , G06F2217/78 , G06F2217/84
摘要： In the present invention a method to address voltage drop effect in the path based timing analysis for multi-phase sequential circuit is proposed. In calculating the new delay of the gate along the specified path the fact that stored discrete arrival times with respect to different clock phases at each node is used to determine a set of gates that can have transitions overlapping with that of the said gate. Furthermore, the said set is reduced by the logic verification step. Two step approach is adopted, the first is to evaluate the power currents for the said reduced set of gates by using pre-characterized timing library, then use these currents to calculate new VDD of the said gate along the path and obtain new delay for this gate. Some cell may have several internal transitions, the process of modeling power currents in terms of several triangles is discussed.
摘要翻译：在本发明中，提出了一种解决多相顺序电路基于路径的时序分析中的电压降效应的方法。在计算栅极沿着指定路径的新延迟时，使用相对于每个节点处的不同时钟相位的存储的离散到达时间来确定可以具有与所述门的跳变重叠的转换的一组门。此外，所述组由逻辑验证步骤减少。采用两步法，首先是通过使用预定义的定时库来评估所述减小的门组的功率电流，然后使用这些电流来计算沿着路径的所述门的新的VDD，并为此获得新的延迟门。一些电池可能有几个内部转换，讨论了几个三角形对功率电流建模的过程。

2. 发明申请

US20080320425A1 Method for Verifying Timing of a Circuit with RLC Inputs and Outputs 有权
标题翻译：使用RLC输入和输出验证电路的时序的方法
公开(公告)号：US20080320425A1
公开(公告)日：2008-12-25
申请号：US12186472
申请日：2008-08-05
申请人： Mau-Chung Chang
发明人： Mau-Chung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5022 , G06F17/5036 , G06F2217/84
摘要： A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g. complex gate, for timing characterization, (d) Circuit structures at transistor level solved by incorporating function check, (e) Carrying out functional check to filter out failing path and identifying gate with simultaneously changing inputs, (f) Finding maximum operation frequency in the presence of level sensitive latches after filtering out false paths, (g) Crosstalk solver by utilizing the admittance matrix and voltage transfer of RLC part in frequency domain coupled with the non-linear driver in time domain implemented in spice-like simulator, (h) Making use of the correlation between inputs of aggressors and victim to determine switching time at victim's output iteratively.
摘要翻译：单一的验证工具提供了在统一的环境中针对全定制和ASIC设计的静态时序分析和时序仿真功能。在各种实施例中，验证工具包括以下特征：（a）将静态时序分析和动态仿真工具集成到单个工具中，（b）在存在的情况下对多相，多频和多周期电路进行高效路径搜索的电平敏感锁存器，（c）自动识别电路结构，例如复合门，用于定时表征，（d）通过并入功能检查来解决晶体管级的电路结构，（e）进行功能检查以滤除故障路径并识别具有同时变化的输入的门，（f）找到最大工作频率（g）通过利用导频矩阵和频域中的RLC部分与非线性驱动器中的时间域中的非线性驱动器的电压传输，在滤波掉伪路径之后存在电平敏感锁存器，（h）利用侵略者和受害者的输入之间的相关性来迭代地确定受害者输出的切换时间。

3. 发明申请

US20060200786A1 Static timing analysis and dynamic simulation for custom and ASIC designs 有权
公开(公告)号：US20060200786A1
公开(公告)日：2006-09-07
申请号：US11347029
申请日：2006-02-03
申请人： Mau-Chung Chang
发明人： Mau-Chung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5022 , G06F17/5036 , G06F2217/84
摘要： A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g. complex gate, for timing characterization, (d) Circuit structures at transistor level solved by incorporating function check, (e) Carrying out functional check to filter out failing path and identifying gate with simultaneously changing inputs, (f) Finding maximum operation frequency in the presence of level sensitive latches after filtering out false paths, (g) Crosstalk solver by utilizing the admittance matrix and voltage transfer of RLC part in frequency domain coupled with the non-linear driver in time domain implemented in spice-like simulator, (h) Making use of the correlation between inputs of aggressors and victim to determine switching time at victim's output iteratively.

4. 发明申请

US20080307375A1 Method for Performing Timing Analysis of a Circuit 有权
标题翻译：执行电路定时分析的方法
公开(公告)号：US20080307375A1
公开(公告)日：2008-12-11
申请号：US12186431
申请日：2008-08-05
申请人： Mau-Chung Chang
发明人： Mau-Chung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5022 , G06F17/5036 , G06F2217/84
摘要： A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g. complex gate, for timing characterization, (d) Circuit structures at transistor level solved by incorporating function check, (e) Carrying out functional check to filter out failing path and identifying gate with simultaneously changing inputs, (f) Finding maximum operation frequency in the presence of level sensitive latches after filtering out false paths, (g) Crosstalk solver by utilizing the admittance matrix and voltage transfer of RLC part in frequency domain coupled with the non-linear driver in time domain implemented in spice-like simulator, (h) Making use of the correlation between inputs of aggressors and victim to determine switching time at victim's output iteratively.
摘要翻译：单一的验证工具提供了在统一的环境中针对全定制和ASIC设计的静态时序分析和时序仿真功能。在各种实施例中，验证工具包括以下特征：（a）将静态时序分析和动态仿真工具集成到单个工具中，（b）在存在的情况下对多相，多频和多周期电路进行高效路径搜索的电平敏感锁存器，（c）自动识别电路结构，例如复合门，用于定时表征，（d）通过并入功能检查来解决晶体管级的电路结构，（e）进行功能检查以滤除故障路径并识别具有同时变化的输入的门，（f）找到最大工作频率（g）通过利用导频矩阵和频域中的RLC部分与非线性驱动器中的时间域中的非线性驱动器的电压传输，在滤波掉伪路径之后存在电平敏感锁存器，（h）利用侵略者和受害者的输入之间的相关性来迭代地确定受害者输出的切换时间。

5. 发明申请

US20060014509A1 Adaptive-biased mixer 有权
标题翻译：自适应偏置混频器
公开(公告)号：US20060014509A1
公开(公告)日：2006-01-19
申请号：US10890712
申请日：2004-07-14
申请人： Zhiwei Xu , Pei-Ming Chow , Mau-Chung Chang
发明人： Zhiwei Xu , Pei-Ming Chow , Mau-Chung Chang
IPC分类号： H04B1/06 , H04B7/00
CPC分类号： H03D7/1441 , H03D7/1433 , H03D7/1458 , H03D7/1491 , H03D7/165 , H03D2200/0043 , H03D2200/0047 , H03D2200/0084
摘要： A system or method for a circuit network that receives an RF signal, and where a plurality of switching transistors receive an RF signal output by the circuit network and perform mixing with a local oscillation (LO) signal received on a LO input. An active bias circuit performs active bias of the plurality of switching transistors in a feedback loop provided between the LO input and an output of the plurality of switching transistors.
摘要翻译：一种用于接收RF信号的电路网络的系统或方法，其中多个开关晶体管接收由电路网络输出的RF信号，并且与在LO输入端接收的本地振荡（LO）信号进行混频。有源偏置电路在LO输入和多个开关晶体管的输出之间的反馈环路中执行多个开关晶体管的有源偏置。

6. 发明授权

US10325047B2 Power network reduction and simulation in time and frequency domains to calculate voltage drop 有权
公开(公告)号：US10325047B2
公开(公告)日：2019-06-18
申请号：US14872153
申请日：2015-10-01
申请人： Mau-chung Chang
发明人： Mau-chung Chang
IPC分类号： G06F17/50
摘要： In the present invention the issue of calculating voltage drop at the contact points of the power network with injected power currents is proposed. The method consists of the three steps. First, the said power network is partitioned into sub-networks. Secondly, the said sub-networks are expressed in terms of their admittance matrices and voltage transfer functions, which are then fed into timing simulator handling both time and frequency to compute the voltage drop at the said contact points. To achieve better partition result, inputs, outputs including user assigned nodes for recording voltages, are utilized to absorb the sub-network without inputs and outputs into the same partition as its parent node, and generate output cone with single input and outputs. Timing simulator uses convolution to get input voltage at each time step recursively and then voltage transfer used to evaluate output voltage at the same time step with minimal computational overhead.

7. 发明授权

US09898564B2 SSTA with non-gaussian variation to second order for multi-phase sequential circuit with interconnect effect 有权
公开(公告)号：US09898564B2
公开(公告)日：2018-02-20
申请号：US14591852
申请日：2015-01-07
申请人： Mau-chung Chang
发明人： Mau-chung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5022 , G06F17/5045
摘要： In the present invention the issue of SSTA in multi-phase sequential circuit with cross-talk in consideration of non-uniform timing constraint and process variations up to the 2nd order is proposed. Use forward breadth first search to calculate the accumulated probabilities at each node for clock phases and edge probability with respect to input and output clock phases, followed by backward depth first traversal to find all critical paths with their probabilities greater than user specified threshold. A method is proposed to pre-characterize the timing library including second order variations. For cross-talk, the poles and residues of admittance matrix and voltage transfer are carried out to 2nd order variations. Effective capacitances and waveforms at interconnect input or driver's immediate output are calculated to 2nd order variations. Delays at victim outputs are then calculated to 2nd order variations and fed back to SSTA, the probability of path occurrence can be calculated accurately.

8. 发明授权

US08001502B2 Method for performing timing analysis of a circuit 有权
标题翻译：执行电路定时分析的方法
公开(公告)号：US08001502B2
公开(公告)日：2011-08-16
申请号：US12186431
申请日：2008-08-05
申请人： Mau-Chung Chang
发明人： Mau-Chung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5022 , G06F17/5036 , G06F2217/84
摘要： A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g. complex gate, for timing characterization, (d) Circuit structures at transistor level solved by incorporating function check, (e) Carrying out functional check to filter out false path and identifying gate with simultaneously changing inputs, (f) Finding maximum operating frequency in the presence of level sensitive latches after filtering out false paths, (g) Crosstalk solver by utilizing the admittance matrix and voltage transfer of RLC part in frequency domain coupled with the non-linear driver in time domain implemented in spice-like simulator, (h) Making use of the correlation between inputs of aggressors and victim to determine switching time at victim's output iteratively.
摘要翻译：单一的验证工具提供了在统一的环境中针对全定制和ASIC设计的静态时序分析和时序仿真功能。在各种实施例中，验证工具包括以下特征：（a）将静态时序分析和动态仿真工具集成到单个工具中，（b）在存在的情况下对多相，多频和多周期电路进行高效路径搜索的电平敏感锁存器，（c）自动识别电路结构，例如复合门，用于定时表征，（d）通过并入功能检查来解决晶体管级的电路结构，（e）进行功能检查以滤除错误路径并识别门，同时改变输入，（f）在最大工作频率（g）通过利用导频矩阵和频域中的RLC部分与非线性驱动器中的时间域中的非线性驱动器的电压传输，在滤波掉伪路径之后存在电平敏感锁存器，（h）利用侵略者和受害者的输入之间的相关性来迭代地确定受害者输出的切换时间。

9. 发明授权

US07895543B2 Method for verifying timing of a circuit with RLC inputs and outputs 有权
标题翻译：用于验证具有RLC输入和输出的电路的定时的方法
公开(公告)号：US07895543B2
公开(公告)日：2011-02-22
申请号：US12186472
申请日：2008-08-05
申请人： Mau-Chung Chang
发明人： Mau-Chung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5022 , G06F17/5036 , G06F2217/84
摘要： A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g. complex gate, for timing characterization, (d) Circuit structures at transistor level solved by incorporating function check, (e) Carrying out functional check to filter out false path and identifying gate with simultaneously changing inputs, (f) Finding maximum operating frequency in the presence of level sensitive latches after filtering out false paths, (g) Crosstalk solver by utilizing the admittance matrix and voltage transfer of RLC part in frequency domain coupled with the non-linear driver in time domain implemented in spice-like simulator, (h) Making use of the correlation between inputs of aggressors and victim to determine switching time at victim's output iteratively.
摘要翻译：单一的验证工具提供了在统一的环境中针对全定制和ASIC设计的静态时序分析和时序仿真功能。在各种实施例中，验证工具包括以下特征：（a）将静态时序分析和动态仿真工具集成到单个工具中，（b）在存在的情况下对多相，多频和多周期电路进行高效路径搜索的电平敏感锁存器，（c）自动识别电路结构，例如复合门，用于定时表征，（d）通过并入功能检查来解决晶体管级的电路结构，（e）进行功能检查以滤除错误路径并识别门，同时改变输入，（f）在最大工作频率（g）通过利用导频矩阵和频域中的RLC部分与非线性驱动器中的时间域中的非线性驱动器的电压传输，在滤波掉伪路径之后存在电平敏感锁存器，（h）利用侵略者和受害者的输入之间的相关性来迭代地确定受害者输出的切换时间。

10. 发明授权

US07650583B2 Method for determining maximum operating frequency of a filtered circuit 有权
标题翻译：确定滤波电路最大工作频率的方法
公开(公告)号：US07650583B2
公开(公告)日：2010-01-19
申请号：US12186467
申请日：2008-08-05
申请人： Mau-Chung Chang
发明人： Mau-Chung Chang
IPC分类号： G06F17/50
CPC分类号： G06F17/5031 , G06F17/5022 , G06F17/5036 , G06F2217/84
摘要： A single verification tool provides both static timing analysis and timing simulation capabilities targeted at both full-custom and ASIC designs in a unified environment. In various embodiments the verification tool includes the following features: (a) Integrating both static timing analysis and dynamic simulation tools into a single tool, (b) Efficient path search for multi-phase, multi-frequency and multi-cycle circuit in the presence of level sensitive latch, (c) Automatically identifying circuit structure, e.g. complex gate, for timing characterization, (d) Circuit structures at transistor level solved by incorporating function check, (e) Carrying out functional check to filter out false path and identifying gate with simultaneously changing inputs, (f) Finding maximum operating frequency in the presence of level sensitive latches after filtering out false paths, (g) Crosstalk solver by utilizing the admittance matrix and voltage transfer of RLC part in frequency domain coupled with the non-linear driver in time domain implemented in spice-like simulator, (h) Making use of the correlation between inputs of aggressors and victim to determine switching time at victim's output iteratively.
摘要翻译：单一的验证工具提供了在统一的环境中针对全定制和ASIC设计的静态时序分析和时序仿真功能。在各种实施例中，验证工具包括以下特征：（a）将静态时序分析和动态仿真工具集成到单个工具中，（b）在存在的情况下对多相，多频和多周期电路进行高效路径搜索的电平敏感锁存器，（c）自动识别电路结构，例如复合门，用于定时表征，（d）通过并入功能检查来解决晶体管级的电路结构，（e）进行功能检查以滤除错误路径并识别门，同时改变输入，（f）在最大工作频率（g）通过利用导频矩阵和频域中的RLC部分与非线性驱动器中的时间域中的非线性驱动器的电压传输，在滤波掉伪路径之后存在电平敏感锁存器，（h）利用侵略者和受害者的输入之间的相关性来迭代地确定受害者输出的切换时间。

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