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1. 发明授权

US5440453A Extended architecture for FPGA 失效
标题翻译： FPGA扩展体系结构
公开(公告)号：US5440453A
公开(公告)日：1995-08-08
申请号：US152267
申请日：1993-11-12
申请人： Laurance H. Cooke , Matthew D. Penry
发明人： Laurance H. Cooke , Matthew D. Penry
IPC分类号： H01L25/18 , G06F1/18 , H01L23/50 , H01L23/52 , H01L25/10 , H01L25/11 , H01R23/68
CPC分类号： G06F1/18
摘要： The invention provides a packaging technique implementing an electronic circuit, comprising several individually packaged sub-circuits, on a circuit board within the footprint of a single package. The embodiment of the present invention is particularly advantageous when implementing application specific integrated circuits (ASICs) or field programmable gate arrays (FPGAs). Selected pins of an upper package are electrically coupled to corresponding pins of the next lower adjacent package such that the pins of the uppermost package can be coupled to the pins of the lowermost package and correspondingly to the signal leads and power bus conductors of the printed circuit board. Portions of selected pins may be removed from one or more packages prior to forming the stacked structure to electrically isolate corresponding pins of upper packages from the pins of lower packages. A template is provided that permits rapid identification of pins to be removed before the packages are configured in the stack.Careful partitioning of the electrical circuit permits a limited number of standard bonding patterns to be combined in a large variety of configurations by rotating packages relative to adjacent packages in the stack. Each package is also provided with additional pins that may be used for vertical routing in a manner that couples non-adjacent packages without coupling to intervening packages. Heat sinks and heat pipes are attachable to the stack to increase thermal dissipation.
摘要翻译：本发明提供一种实现电子电路的封装技术，该电子电路包括几个单独封装的子电路，位于单个封装的封装内的电路板上。当实现专用集成电路（ASIC）或现场可编程门阵列（FPGA）时，本发明的实施例是特别有利的。上部封装的选定引脚电耦合到下一个相邻封装的相应引脚，使得最上面的封装的引脚可以耦合到最下面封装的引脚，并且对应于印刷电路的信号引线和电源总线导体板。所选引脚的部分可以在形成堆叠结构之前从一个或多个封装去除，以将上部封装的相应引脚与下部封装的引脚隔离。提供了一个模板，可以在堆叠配置包之前快速识别要删除的引脚。仔细分割电路允许通过相对于堆叠中的相邻封装件旋转封装而将有限数量的标准焊接图案组合在各种配置中。每个包装还具有附加销，其可以以不连接到中间包装的方式耦合不相邻包装的方式用于垂直布线。散热器和热管可附接到堆叠以增加散热。

2. 发明授权

US6049094A Low stress package assembly for silicon-backed light valves 失效
标题翻译：用于硅背光阀的低应力包装组件
公开(公告)号：US6049094A
公开(公告)日：2000-04-11
申请号：US82900
申请日：1998-05-21
申请人： Matthew D. Penry
发明人： Matthew D. Penry
IPC分类号： G02F1/03 , G02F1/13 , H01L33/00 , H01L23/29 , H01L23/495
CPC分类号： G02F1/133308 , G02F1/0305 , G02F2202/28 , H01L2224/48091 , H01L2224/73265
摘要： A low-stress silicon-backed light valve package assembly that includes a matched coefficient of thermal expansion (CTE) substrate with a CTE no greater than 300% of the CTE of silicon, a silicon-backed light valve adhered to the matched CTE substrate by a soft adhesive layer, a flexible circuit adhered to the matched CTE substrate and electrically connected to the silicon-backed light valve, an encapsulant dam surrounding the silicon-backed light valve and a soft encapsulant layer filling the cavity defined by the encapsulant dam. Both the soft encapsulant layer and the soft adhesive layer have a Shore A hardness of less than 5. The combination of a soft encapsulant layer, soft adhesive layer and matched CTE substrate insure sufficiently low mechanical stress levels to avoid the presence of optical interference patterns in the light valve display.
摘要翻译：低应力硅背光阀封装组件，其包括匹配的热膨胀系数（CTE）衬底，CTE不超过硅的CTE的300％，硅背光阀通过附着在匹配的CTE衬底上的硅背光阀柔性粘合剂层，柔性电路粘附到匹配的CTE基板并电连接到硅背光阀，围绕硅背光阀的密封剂坝和填充由密封剂坝限定的空腔的软包封层。软密封剂层和软粘合剂层的肖氏A硬度都小于5.软密封剂层，软粘合剂层和匹配的CTE基材的组合确保足够低的机械应力水平以避免光学干涉图案的存在光阀显示。

3. 发明授权

US5132773A Carrier ring having first and second ring means with bonded surfaces 失效
标题翻译：带有接合表面的第一和第二环的承载环
公开(公告)号：US5132773A
公开(公告)日：1992-07-21
申请号：US651686
申请日：1991-02-06
申请人： Jeffrey S. Braden , Matthew D. Penry
发明人： Jeffrey S. Braden , Matthew D. Penry
IPC分类号： H01L21/56 , H01L23/00 , H01L23/28 , H01L23/495 , H01L23/50
CPC分类号： H01L23/562 , H01L23/49558 , H01L2224/45147 , H01L2224/48091 , H01L2224/48247 , H01L24/45 , H01L24/48 , H01L2924/00014 , H01L2924/01014 , H01L2924/14 , H01L2924/181
摘要： A two-piece carrier ring is provided. First and second rings are affixed to opposing sides of the exterior portion of a leadframe and protect the leads from distortion. The rings are molded prior to bonding to the leadframe so that the rings may be formed from a wide variety of plastics. The premolded rings are polymerized prior to bonding preventing distortion of the leads by shrinking of the rings.
摘要翻译：提供两片式载体环。第一和第二环固定在引线框架的外部部分的相对侧上并保护引线不变形。在结合到引线框架之前将环模制成环，使得环可以由各种各样的塑料形成。预结合的环在接合之前被聚合，从而防止环的收缩导致引线的变形。

4. 发明授权

US06984866B1 Flip chip optical semiconductor on a PCB 有权
标题翻译：在PCB上倒装芯片光学半导体
公开(公告)号：US06984866B1
公开(公告)日：2006-01-10
申请号：US10391283
申请日：2003-03-17
申请人： Shahram Mostafazadeh , Joseph O. Smith , Matthew D. Penry
发明人： Shahram Mostafazadeh , Joseph O. Smith , Matthew D. Penry
IPC分类号： H01L31/0203
CPC分类号： H01L31/0203 , H01L27/14618 , H01L2924/15192
摘要： Semiconductor devices and methods for making semiconductor devices. The present invention allows a flip chip assembly to be used with an optical semiconductor device. The optical semiconductor flip chip is positioned over a hole in a PCB such that the imaging area of the optical semiconductor flip chip faces the hole. The hole allows the imaging area to be unobstructed by the PCB. Underfill material can be prevented from going into the hole by erecting a barrier on top of the PCB that surrounds the hole.
摘要翻译：用于制造半导体器件的半导体器件和方法。本发明允许与光学半导体器件一起使用倒装芯片组件。光学半导体倒装芯片位于PCB中的孔的上方，使得光学半导体倒装芯片的成像区域面向孔。该孔允许成像区域被PCB阻挡。可以通过在围绕孔的PCB的顶部上竖立阻挡层来防止底部填充材料进入孔中。

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