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1. 发明申请

US20100230782A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20100230782A1
公开(公告)日：2010-09-16
申请号：US12721151
申请日：2010-03-10
申请人： Shinichi UCHIDA , Masayuki FURUMIYA , Hiroshi SAKAKIBARA , Takashi IWADARE , Yoshiyuki SATO , Makoto EGUCHI , Masato TAKI , Hidetoshi MORISHITA , Kozo KATO , Jun MORIMOTO
发明人： Shinichi UCHIDA , Masayuki FURUMIYA , Hiroshi SAKAKIBARA , Takashi IWADARE , Yoshiyuki SATO , Makoto EGUCHI , Masato TAKI , Hidetoshi MORISHITA , Kozo KATO , Jun MORIMOTO
IPC分类号： H01L23/522 , H01L29/86
CPC分类号： H01L23/5227 , H01L23/48 , H01L23/49822 , H01L23/645 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/05624 , H01L2224/05647 , H01L2224/48137 , H01L2224/48145 , H01L2224/49052 , H01L2224/49175 , H01L2224/4943 , H01L2225/06506 , H01L2225/06527 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/10329 , H01L2924/12041 , H01L2924/19042 , H01L2924/30107 , H04L25/0266 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire.
摘要翻译：第一半导体芯片包括第一电感器和第二电感器，第二半导体芯片包括第三电感器和第四电感器。第一电感器连接到第一半导体芯片的第一接收电路，第二电感器通过第一接合线连接到第二半导体芯片的第二发送电路。第三电感器连接到第二半导体芯片的第二接收电路，第四电感器通过第二接合线连接到第一半导体芯片的第一发送电路。

2. 发明申请

US20100124125A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20100124125A1
公开(公告)日：2010-05-20
申请号：US12619952
申请日：2009-11-17
申请人： Masakazu AMANAI , Masahiko KASHIMURA , Yoshihiro NAGAI , Masato TAKI , Norihiro HONDA , Kazushi YAMANAKA
发明人： Masakazu AMANAI , Masahiko KASHIMURA , Yoshihiro NAGAI , Masato TAKI , Norihiro HONDA , Kazushi YAMANAKA
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/28
摘要： A nonvolatile memory device includes a memory cell that stores data by presence or absence of electrons accumulated in a floating gate, a read reference current generator that generates a read reference current for reading data from the memory cell based on a constant current from a constant current generator included therein, and a read voltage generator that generates a read voltage to be applied to a control gate of the memory cell during data reading. The read reference current generator generates a monitor voltage that varies according to variation of the read reference current and a threshold voltage of the memory cell. The read voltage generator generates the read voltage based on the monitor voltage.
摘要翻译：非易失性存储器件包括存储单元，其通过存在或不存在在浮置栅极中累积的电子来存储数据;读取参考电流发生器，其基于来自恒定电流的恒定电流产生用于从存储器单元读取数据的读取参考电流以及读取电压发生器，其在数据读取期间产生要施加到存储器单元的控制栅极的读取电压。读取的参考电流发生器产生根据读取的参考电流的变化和存储器单元的阈值电压而变化的监视电压。读取电压发生器根据监视电压产生读取电压。

3. 发明申请

US20070085595A1 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US20070085595A1
公开(公告)日：2007-04-19
申请号：US10576292
申请日：2004-10-08
申请人： Masato Taki , Hideki Tojima
发明人： Masato Taki , Hideki Tojima
IPC分类号： H03K3/01
CPC分类号： H01L29/7816 , H01L27/092 , H01L29/0615 , H01L29/0649 , H01L29/0653 , H01L29/408 , H01L29/7824 , H01L29/7835
摘要： A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.
摘要翻译：半导体装置（100）包括低电位基准电路区域（1）和高电位基准电路区域（2），高电位基准电路区域（2）由高耐压分离区域（3）包围。通过形成在高耐压分离区域（3）的外周的沟槽（4），低电位基准电路区域（1）和高电位基准电路区域（2）彼此分离。此外，沟槽（4）填充有绝缘材料，并使低电位参考电路区域（1）和高电位参考电路区域（2）绝缘。高耐压分离区域（3）由沟槽（4）分隔开，在分隔位置设有高耐压NMOS（5）或高耐压PMOS（6）。

4. 发明授权

US08373251B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US08373251B2
公开(公告)日：2013-02-12
申请号：US12721151
申请日：2010-03-10
申请人： Shinichi Uchida , Masayuki Furumiya , Hiroshi Sakakibara , Takashi Iwadare , Yoshiyuki Sato , Makoto Eguchi , Masato Taki , Hidetoshi Morishita , Kozo Kato , Jun Morimoto
发明人： Shinichi Uchida , Masayuki Furumiya , Hiroshi Sakakibara , Takashi Iwadare , Yoshiyuki Sato , Makoto Eguchi , Masato Taki , Hidetoshi Morishita , Kozo Kato , Jun Morimoto
IPC分类号： H01L27/08
CPC分类号： H01L23/5227 , H01L23/48 , H01L23/49822 , H01L23/645 , H01L24/06 , H01L24/48 , H01L24/49 , H01L25/0655 , H01L2224/05624 , H01L2224/05647 , H01L2224/48137 , H01L2224/48145 , H01L2224/49052 , H01L2224/49175 , H01L2224/4943 , H01L2225/06506 , H01L2225/06527 , H01L2924/00014 , H01L2924/01004 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01033 , H01L2924/01079 , H01L2924/10329 , H01L2924/12041 , H01L2924/19042 , H01L2924/30107 , H04L25/0266 , H01L2924/00 , H01L2224/45099 , H01L2924/00012
摘要： A first semiconductor chip includes a first inductor and a second inductor, and a second semiconductor chip includes a third inductor and a fourth inductor. The first inductor is connected to a first receiving circuit of the first semiconductor chip, and the second inductor is connected to a second transmitting circuit of the second semiconductor chip through a first bonding wire. The third inductor is connected to a second receiving circuit of the second semiconductor chip, and the fourth inductor is connected to a first transmitting circuit of the first semiconductor chip through a second bonding wire.
摘要翻译：第一半导体芯片包括第一电感器和第二电感器，第二半导体芯片包括第三电感器和第四电感器。第一电感器连接到第一半导体芯片的第一接收电路，第二电感器通过第一接合线连接到第二半导体芯片的第二发送电路。第三电感器连接到第二半导体芯片的第二接收电路，第四电感器通过第二接合线连接到第一半导体芯片的第一发送电路。

5. 发明授权

US07943957B2 Lateral SOI semiconductor devices and manufacturing method thereof 有权
标题翻译：横向SOI半导体器件及其制造方法
公开(公告)号：US07943957B2
公开(公告)日：2011-05-17
申请号：US12097811
申请日：2006-11-17
申请人： Masato Taki , Masahiro Kawakami , Kiyoharu Hayakawa , Masayasu Ishiko
发明人： Masato Taki , Masahiro Kawakami , Kiyoharu Hayakawa , Masayasu Ishiko
IPC分类号： H01L29/861
CPC分类号： H01L29/8611 , H01L21/266 , H01L29/0634 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1608 , H01L29/20 , H01L29/24 , H01L29/402 , H01L29/66128 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835 , H01L29/78624
摘要： A diode 10 comprises an SOI substrate in which are stacked a semiconductor substrate 20, an insulator film 30, and a semiconductor layer 40. A bottom semiconductor region 60, an intermediate semiconductor region 53, and a surface semiconductor region 54 are formed in the semiconductor layer 40. The bottom semiconductor region 60 includes a high concentration of n-type impurity. The intermediate semiconductor region 53 includes a low concentration of n-type impurity. The surface semiconductor region 54 includes p-type impurity.
摘要翻译：二极管10包括层叠有半导体衬底20，绝缘体膜30和半导体层40的SOI衬底。在半导体中形成底部半导体区域60，中间半导体区域53和表面半导体区域54 底部半导体区域60包括高浓度的n型杂质。中间半导体区域53包括低浓度的n型杂质。表面半导体区域54包括p型杂质。

6. 发明申请

US20090184370A1 LATERAL SOI SEMICONDUCTOR DEVICES AND MANUFACTURING METHOD THEREOF 有权
标题翻译：横向SOI半导体器件及其制造方法
公开(公告)号：US20090184370A1
公开(公告)日：2009-07-23
申请号：US12097811
申请日：2006-11-17
申请人： Masato Taki , Masahiro Kawakami , Kiyoharu Hayakawa , Masayasu Ishiko
发明人： Masato Taki , Masahiro Kawakami , Kiyoharu Hayakawa , Masayasu Ishiko
IPC分类号： H01L29/36 , H01L21/762
CPC分类号： H01L29/8611 , H01L21/266 , H01L29/0634 , H01L29/0878 , H01L29/1045 , H01L29/1083 , H01L29/1608 , H01L29/20 , H01L29/24 , H01L29/402 , H01L29/66128 , H01L29/66659 , H01L29/66681 , H01L29/7824 , H01L29/7835 , H01L29/78624
摘要： A diode 10 comprises an SOI substrate in which are stacked a semiconductor substrate 20, an insulator film 30, and a semiconductor layer 40. A bottom semiconductor region 60, an intermediate semiconductor region 53, and a surface semiconductor region 54 are formed in the semiconductor layer 40. The bottom semiconductor region 60 includes a high concentration of n-type impurity. The intermediate semiconductor region 53 includes a low concentration of n-type impurity. The surface semiconductor region 54 includes p-type impurity.
摘要翻译：二极管10包括层叠有半导体衬底20，绝缘体膜30和半导体层40的SOI衬底。在半导体中形成底部半导体区域60，中间半导体区域53和表面半导体区域54 底部半导体区域60包括高浓度的n型杂质。中间半导体区域53包括低浓度的n型杂质。表面半导体区域54包括p型杂质。

7. 发明授权

US08004902B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08004902B2
公开(公告)日：2011-08-23
申请号：US12619952
申请日：2009-11-17
申请人： Masakazu Amanai , Masahiko Kashimura , Yoshihiro Nagai , Masato Taki , Norihiro Honda , Kazushi Yamanaka
发明人： Masakazu Amanai , Masahiko Kashimura , Yoshihiro Nagai , Masato Taki , Norihiro Honda , Kazushi Yamanaka
IPC分类号： G11C16/06 , G11C16/04 , G11C5/14
CPC分类号： G11C16/28
摘要： A nonvolatile memory device includes a memory cell that stores data by presence or absence of electrons accumulated in a floating gate, a read reference current generator that generates a read reference current for reading data from the memory cell based on a constant current from a constant current generator included therein, and a read voltage generator that generates a read voltage to be applied to a control gate of the memory cell during data reading. The read reference current generator generates a monitor voltage that varies according to variation of the read reference current and a threshold voltage of the memory cell. The read voltage generator generates the read voltage based on the monitor voltage.
摘要翻译：非易失性存储器件包括存储单元，其通过存在或不存在在浮置栅极中累积的电子来存储数据;读取参考电流发生器，其基于来自恒定电流的恒定电流产生用于从存储器单元读取数据的读取参考电流以及读取电压发生器，其在数据读取期间产生要施加到存储器单元的控制栅极的读取电压。读取的参考电流发生器产生根据读取的参考电流的变化和存储器单元的阈值电压而变化的监视电压。读取电压发生器根据监视电压产生读取电压。

8. 发明申请

US20090243042A1 LATERAL SEMICONDUCTOR DEVICE 审中-公开
标题翻译：横向半导体器件
公开(公告)号：US20090243042A1
公开(公告)日：2009-10-01
申请号：US12408309
申请日：2009-03-20
申请人： Kiyoharu HAYAKAWA , Masato TAKI
发明人： Kiyoharu HAYAKAWA , Masato TAKI
IPC分类号： H01L29/735
CPC分类号： H01L29/7394 , H01L29/0834 , H01L29/36
摘要： A semiconductor device has a first main electrode and a second main electrode that are provided on a semiconductor layer. The semiconductor layer has: an n type first semiconductor region in contact with the first main electrode; a p type second semiconductor region in contact with the second main electrode; and an n type third semiconductor region provided between the first and second semiconductor regions. The third semiconductor region has a first layer and a second layer. The impurity concentration in the first layer is uniform. The second layer has a higher impurity concentration than the first layer that increases in a gradient from the first semiconductor region to the second semiconductor region.
摘要翻译：半导体器件具有设置在半导体层上的第一主电极和第二主电极。半导体层具有与第一主电极接触的n型第一半导体区域; 与第二主电极接触的p型第二半导体区域; 以及设置在第一和第二半导体区域之间的n型第三半导体区域。第三半导体区域具有第一层和第二层。第一层中的杂质浓度是均匀的。第二层比从第一半导体区到第二半导体区的梯度增加的第一层的杂质浓度高。

9. 发明授权

US07538407B2 Semiconductor apparatus 有权
标题翻译：半导体装置
公开(公告)号：US07538407B2
公开(公告)日：2009-05-26
申请号：US10576292
申请日：2004-10-08
申请人： Masato Taki , Hideki Tojima
发明人： Masato Taki , Hideki Tojima
IPC分类号： H01L29/72
CPC分类号： H01L29/7816 , H01L27/092 , H01L29/0615 , H01L29/0649 , H01L29/0653 , H01L29/408 , H01L29/7824 , H01L29/7835
摘要： A semiconductor apparatus (100) comprises a low potential reference circuit region (1) and a high potential reference circuit region (2), and the high potential reference circuit region (2) is surrounded by a high withstand voltage separating region (3). By a trench (4) formed in the outer periphery of the high withstand voltage separating region (3), the low potential reference circuit region (1) and high potential reference circuit region (2) are separated from each other. Further, the trench (4) is filled up with an insulating material, and insulates the low potential reference circuit region (1) and high potential reference circuit region (2). The high withstand voltage separating region (3) is partitioned by the trench (4), high withstand voltage NMOS (5) or high withstand voltage PMOS (6) is provided in the partitioned position.
摘要翻译：半导体装置（100）包括低电位基准电路区域（1）和高电位基准电路区域（2），高电位基准电路区域（2）由高耐压分离区域（3）包围。通过形成在高耐压分离区域（3）的外周的沟槽（4），低电位基准电路区域（1）和高电位基准电路区域（2）彼此分离。此外，沟槽（4）填充有绝缘材料，并使低电位参考电路区域（1）和高电位参考电路区域（2）绝缘。高耐压分离区域（3）由沟槽（4）分隔开，在分隔位置设有高耐压NMOS（5）或高耐压PMOS（6）。

10. 发明授权

US08106703B2 Booster circuit 有权
标题翻译：增压电路
公开(公告)号：US08106703B2
公开(公告)日：2012-01-31
申请号：US12776586
申请日：2010-05-10
申请人： Yoshihiro Nagai , Masakazu Amanai , Masahiko Kashimura , Masato Taki , Norihiro Honda , Kazushi Yamanaka
发明人： Yoshihiro Nagai , Masakazu Amanai , Masahiko Kashimura , Masato Taki , Norihiro Honda , Kazushi Yamanaka
IPC分类号： G05F1/10 , G05F3/02
CPC分类号： H02M3/073 , H02M2003/076
摘要： Booster circuit comprising: first transistor that is connected to first node; capacitor that has one end connected to first node, and that is charged with voltage of first node when first transistor is activated; and control signal generating circuit that provides control terminal of first transistor with control signal being in accordance with first clock, wherein when first transistor is de-activated, capacitor boosts voltage of first node to first voltage by voltage being applied to or end of capacitor, voltage applied to or end being at least ½ as great as first supply voltage, and control signal generating circuit sets voltage of control signal when first transistor is de-activated to be first voltage of first node, and sets voltage of control signal when first transistor is activated to be voltage, difference between voltage and first voltage being equal to or smaller than value of first supply voltage.
摘要翻译：加速电路，包括：连接到第一节点的第一晶体管; 电容器，其一端连接到第一节点，并且当第一晶体管被激活时被充满第一节点的电压; 以及控制信号发生电路，其向第一晶体管的控制端提供与第一时钟相关的控制信号，其中当第一晶体管被去激活时，电容器通过施加到电容器的电压或其末端的电压将第一节点的电压提升为第一电压，施加到或终止的电压至少为第一电源电压的1/2，并且当第一晶体管被去激活时，控制信号发生电路将控制信号的电压设置为第一节点的第一电压，并且当第一晶体管被激活为电压，电压和第一电压之间的差等于或小于第一电源电压的值。

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