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1. 发明授权

US5835426A Redundant circuit 失效
标题翻译：冗余电路
公开(公告)号：US5835426A
公开(公告)日：1998-11-10
申请号：US968068
申请日：1997-11-12
申请人： Masato Koura
发明人： Masato Koura
IPC分类号： G11C16/02 , G11C16/06 , G11C29/00 , G11C29/04
CPC分类号： G11C29/789
摘要： The present invention includes a redundant circuit for addressing redundant memory cells. The redundant circuit solves a problem of a conventional redundant circuit caused by injection of electrons into and leakage of electrons from a floating gate of a non-volatile memory cells provided for respective bits of the addressing circuit of the redundant circuit. The redundant circuit has a timer that counts an elapsed time from power-on of the redundant circuit. The timer produces a timing signal when a fixed duration time period has elapsed. A breaker breaks the application of a supply voltage to the gate of a non-volatile memory cell in response to the timing signal.
摘要翻译：本发明包括用于寻址冗余存储器单元的冗余电路。冗余电路解决了由为冗余电路的寻址电路的各个位提供的非易失性存储器单元的浮置栅极注入电子和电子泄漏而导致的常规冗余电路的问题。冗余电路具有对从冗余电路上电开始的经过时间进行计数的定时器。当经过固定持续时间时，定时器产生定时信号。响应于定时信号，断路器断开向非易失性存储单元的栅极施加电源电压。

2. 发明授权

US5535379A Timer apparatus capable of writing identical data to a plurality of timers built in a microcomputer 失效
标题翻译：定时器装置能够将相同的数据写入到微计算机内置的多个定时器中
公开(公告)号：US5535379A
公开(公告)日：1996-07-09
申请号：US289449
申请日：1994-08-12
申请人： Masato Koura
发明人： Masato Koura
IPC分类号： G06F1/14 , G06F1/10 , G06F15/78 , H03K17/296 , H03K21/02
CPC分类号： G06F1/10
摘要： A timer apparatus which is provided with a control circuit 80, annexed to each of timers 1-1, 1-2 and 1-3 generating a control signal making the register 3 write data outputted from a CPU 50 when both a write signal 5 generated by the CPU 50 for writing data into the registers 3, and a timer single write signal 11 for specifying any of the timers, are generated, and furthermore is provided with a selection circuit 70 making each control circuit 80 generate a control signal when both the write signal 5 and a timer grouping signal 14 generated for specifying each of the plurality of timers 1-1, 1-2 and 1-3, are generated. When it is necessary that identical data be held in the respective registers 3 of the plurality of timers 1-1, 1-2 and 1-3, the identical data can be written into each of the registers 3 at the same time.
摘要翻译：定时器装置设有控制电路80，每个定时器1-1,1-2和1-3附加到控制电路80，产生一个控制信号，使得寄存器3在写入信号5产生时写入从CPU50输出的数据通过用于将数据写入寄存器3的CPU 50，并且生成用于指定任何定时器的定时器单个写入信号11，并且还设置有选择电路70，使得每个控制电路80在两者生成用于指定多个定时器1-1,1-2和1-3中的每一个的写入信号5和定时器分组信号14。当需要在多个定时器1-1,1-2和1-3的各个寄存器3中保持相同的数据时，可以将相同的数据同时写入每个寄存器3。

3. 发明授权

US6069833A Voltage drop circuit enabling ROM to read data with high reliability 失效
标题翻译：电压降电路使ROM能够高可靠性地读取数据
公开(公告)号：US6069833A
公开(公告)日：2000-05-30
申请号：US304666
申请日：1999-05-04
申请人： Masato Koura
发明人： Masato Koura
IPC分类号： G06F12/16 , G05F1/56 , G11C5/14 , G11C8/00
CPC分类号： G11C5/147
摘要： A voltage drop circuit for generating an active voltage to be supplied to a ROM by dropping a supply voltage. The voltage drop circuit inhibits an access of a CPU to the ROM for a predetermined time period immediately after the ROM shifts from a standby mode to an active mode. This makes it possible to solve a problem of a conventional voltage drop circuit in that it is not unlikely that the CPU cannot read data correctly from the ROM for a moment immediately after the ROM shifts from the standby mode to the active mode because of fluctuations of the active voltage in that moment.
摘要翻译：一种用于通过降低电源电压来产生要提供给ROM的有效电压的电压降电路。电压降电路在ROM从待机模式切换到活动模式之后，在紧接着预定时间段之后禁止CPU访问ROM。这使得可以解决传统的电压降电路的问题，因为在ROM从待机模式转换到活动模式之后，CPU不能从ROM中正确读取数据一段时间，这是因为波动该时刻的有功电压。

4. 发明授权

US5826059A Microcomputer for emulation 失效
标题翻译：微电脑仿真
公开(公告)号：US5826059A
公开(公告)日：1998-10-20
申请号：US574142
申请日：1995-12-18
申请人： Daijiro Harada , Katsunobu Hongo , Masato Koura
发明人： Daijiro Harada , Katsunobu Hongo , Masato Koura
IPC分类号： G06F11/22 , G06F11/36 , G06F12/06 , G06F15/78 , G06F9/455
CPC分类号： G06F11/3652 , G06F12/0646
摘要： A microcomputer for emulation which has been conventionally unusable when built-in RAM capacities are different, because an access to an internal function circuit is different in bus control, wait condition and the like from the access to an external memory area, and despite the above fact, which now becomes usable by including a built-in RAM 17, a higher address decoder (virtual RAM address decoder) for generating a virtual RAM address space corresponding to a plurality of virtual RAM capacities within a range in which installed capacity of the built-in RAM 17 is made a maximum value, and a RAM capacity selection flag 36 for specifying any one of a plurality of virtual RAM address spaces which can be generated by the higher address decoder 22.
摘要翻译：在内置RAM容量不同的情况下，由于对内部功能电路的访问在总线控制，等待条件等的访问方面与外部存储区域的访问不同，所以通常不能使用的仿真微型计算机，尽管如此事实上，现在可以通过包括内置RAM 17，更高地址解码器（虚拟RAM地址解码器）来生成与多个虚拟RAM容量相对应的虚拟RAM地址空间可用的范围，该范围内的内置RAM - 将RAM17设为最大值，以及RAM容量选择标志36，用于指定可由高地址解码器22产生的多个虚拟RAM地址空间中的任一个。

5. 发明授权

US6111395A Power supply voltage step-down circuitry 失效
标题翻译：电源电压降压电路
公开(公告)号：US6111395A
公开(公告)日：2000-08-29
申请号：US436245
申请日：1999-11-09
申请人： Takuya Hirade , Masato Koura , Katsunobu Hongo
发明人： Takuya Hirade , Masato Koura , Katsunobu Hongo
IPC分类号： G05F1/00 , G05F1/10 , G05F1/46 , G05F1/445
CPC分类号： G05F1/465
摘要： Power supply voltage step-down circuitry comprises a control unit for enabling either a first voltage step-down unit or a second voltage step-down unit according to a control signal applied thereto, a voltage checking unit for checking whether or not the value of a voltage generated by a power supply is equal to or greater than a predetermined value, and for furnishing a checking result signal at a predetermined level when the value of the voltage generated by the power supply is equal to or greater than a predetermined value, and a switching unit for connecting either the power supply or an output of the first step-down unit with a receiver, such as a ROM, according to whether or not the checking result signal from the voltage checking unit is at the predetermined level. The voltage checking unit includes a Schmidt circuit that furnishes the checking result signal at a level corresponding to the value of an output of a checking unit for furnishing the output having a value corresponding to the power supply voltage.
摘要翻译：电源电压降压电路包括：控制单元，用于根据施加的控制信号使第一降压单元或第二降压单元能够实现;电压检查单元，用于检查是否由电源产生的电压等于或大于预定值，并且当由电源产生的电压的值等于或大于预定值时，将检查结果信号提供在预定电平，并且切换单元，用于根据来自电压检查单元的检查结果信号是否处于预定水平，将电源或第一降压单元的输出与诸如ROM的接收器连接。电压检查单元包括施密特电路，其将检查结果信号提供在与检查单元的输出值相对应的电平上，以提供具有与电源电压相对应的值的输出。

6. 发明授权

US06601131B2 Flash memory access control via clock and interrupt management 有权
标题翻译：通过时钟和中断管理进行闪存访问控制
公开(公告)号：US06601131B2
公开(公告)日：2003-07-29
申请号：US09735621
申请日：2000-12-14
申请人： Toshihiro Sezaki , Katsunobu Hongo , Masato Koura
发明人： Toshihiro Sezaki , Katsunobu Hongo , Masato Koura
IPC分类号： G06F1316
CPC分类号： G06F15/7814
摘要： A microcomputer with a built-in flash memory includes a flash controller for controlling writing/erasing of the flash memory in accordance with a command from a CPU. The flash controller produces a CPU rewriting mode designating signal and a busy signal during writing/erasing of the flash memory. In response to the two signals, awaiting mode controller implements a waiting mode by outputting a control signal to open and close an AND gate using the control signal, thereby halting a supply of a clock signal to the CPU in the waiting mode. The microcomputer can reduce the load on software for writing/erasing of the flash memory, and the load on developing software.
摘要翻译：具有内置闪存的微型计算机包括闪存控制器，用于根据来自CPU的命令控制闪存的写入/擦除。闪存控制器在写入/擦除闪存期间产生CPU重写模式指定信号和忙信号。响应于这两个信号，等待模式控制器通过输出控制信号来执行等待模式，以使用控制信号来打开和关闭与门，从而在等待模式中停止向CPU提供时钟信号。微型计算机可以减少软件写入/擦除的负担，以及开发软件的负担。

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