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1. 发明申请

US20110066766A1 CONTROL APPARATUS AND DATA PROCESSING SYSTEM 审中-公开
标题翻译：控制装置和数据处理系统
公开(公告)号：US20110066766A1
公开(公告)日：2011-03-17
申请号：US12873379
申请日：2010-09-01
申请人： Masanobu FURUKOSHI
发明人： Masanobu FURUKOSHI
IPC分类号： G06F3/00
CPC分类号： G06F13/4221
摘要： A control apparatus connectable to a plurality of electronic units via a bus, the control apparatus controlling operations of the plurality of electronic units, the control apparatus includes a first storage section for storing an operating information used for operating each of the plurality of electronic units, a second storage section for storing an identifying information used for identifying each of the electronic units, a controller for controlling to receive a start notification of one of the electronic units, query the one of the electronic units about the identifying information, receive the identifying information from the one of the electronic units, compare the received identifying information with the stored identifying information in the second storage section, and query the one of the electronic units about an operating information when the received identifying information is different from the stored identifying information.
摘要翻译：一种控制装置，其经由总线连接到多个电子单元，所述控制装置控制所述多个电子单元的操作，所述控制装置包括：第一存储部，用于存储用于操作所述多个电子单元中的每一个的操作信息; 用于存储用于识别每个电子单元的识别信息的第二存储部分，用于控制以接收一个电子单元的开始通知的控制器，查询关于识别信息的电子单元中的一个，接收识别信息从所述电子单元中的一个电子单元将所接收的识别信息与所存储的识别信息进行比较，并且当所接收的识别信息与所存储的识别信息不同时，查询所述电子单元之一关于操作信息。

2. 发明授权

US06789176B2 Address release method, and common buffering device for ATM switching system which employs the same method 失效
标题翻译：地址释放方法和采用相同方法的ATM交换系统的通用缓冲装置
公开(公告)号：US06789176B2
公开(公告)日：2004-09-07
申请号：US09286332
申请日：1999-04-05
申请人： Shiro Uriu , Masanobu Furukoshi , Tetsuaki Wakabayashi , Kazumasa Sonoda
发明人： Shiro Uriu , Masanobu Furukoshi , Tetsuaki Wakabayashi , Kazumasa Sonoda
IPC分类号： G06F1206
CPC分类号： H04L12/5601 , H04L49/108 , H04L49/203 , H04L49/255 , H04L2012/5681
摘要： In a common buffering device with a simple arrangement, a write address can be efficiently released from a buffer memory upon receipt of a multi-address call. For an ATM cell which is to be transmitted to a specific line, a write address is set in a common buffer memory, and the ATM cell is written at the write address. The ATM cell is read from an address which corresponds to the write address, and is transmitted to the specific line. Then, the pertinent write address is released. In a write table are entered a plurality of multi-address lines across which an ATM cell written at a specific address in the common buffering device can be multicast. Each time the ATM cell is read from the specific address, a designation line for transmission of an ATM cell in a read control table is compared with the multi-address lines set in the write control table. When the lines match, the write address for the ATM cell, which is set in the write control table, is released.
摘要翻译：在具有简单布置的公共缓冲装置中，在接收到多地址呼叫时，可以从缓冲存储器高效地释放写入地址。对于要发送到特定线路的ATM信元，在公共缓冲存储器中设置写入地址，并且将ATM信元写入写入地址。 ATM单元从对应于写入地址的地址读取，并被发送到特定的行。然后，释放相关的写入地址。在写入表中输入多个多地址线，在公共缓冲设备中以特定地址写入的ATM信元可以跨多路地址线进行组播。每当从特定地址读取ATM信元时，将读取控制表中的ATM信元的发送指定行与设置在写入控制表中的多地址线进行比较。当行匹配时，释放写入控制表中设置的ATM信元的写入地址。

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