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    • 1. 发明专利
    • Display device
    • 显示设备
    • JP2005189276A
    • 2005-07-14
    • JP2003427133
    • 2003-12-24
    • Masamichi Mori正道 森
    • MORI MASAMICHI
    • F21S2/00F21Y101/02G09F13/12
    • PROBLEM TO BE SOLVED: To provide a fantastic and novel display device capable of functioning as a mirror when a light source is turned off and displaying a desired image or scene etc., on a mirror when turned on. SOLUTION: The display device 11 comprises a device main body 12 formed in a prismatic shape of a plurality of side plates by bending a plate material and the light source 13 which is set in the device main body 12; and a 1st side plate 14 among the plurality of side plates 14, 15, and 16 of the device main body 12 is formed into a mirror surface body 19 whose transmissivity is 3 to 7% and equipped with holding members 21a and 21b holding a desired translucent display sheet 20 inside and the 2nd side plate 15 and 3rd side plate 16 are subjected to specified light shield processing to cut off external light and have their inner surfaces 15a and 16a formed into mirror surfaces. COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:提供一种梦幻般的和新颖的显示装置,当打开光源时,在光源被关闭并显示期望的图像或场景等时可以用作反射镜。 解决方案:显示装置11包括通过弯曲板材而形成为多个侧板的棱柱形状的装置主体12和设置在装置主体12中的光源13; 并且装置主体12的多个侧板14,15和16中的第一侧板14形成为透光率为3至7%的镜面体19,并且具有保持所需的保持构件21a和21b 进行内部半透明显示片20和第二侧板15和第三侧板16进行规定的遮光处理以切断外部光,并使其内表面15a和16a形成为镜面。 版权所有(C)2005,JPO&NCIPI
    • 5. 发明授权
    • Low crosstalk type switching matrix of monolithic semiconductor device
    • 单片半导体器件的低串扰型开关矩阵
    • US4246594A
    • 1981-01-20
    • US883796
    • 1978-03-06
    • Masamichi Mori
    • Masamichi Mori
    • H01L29/74H01L21/761H01L27/02H01L27/06H01L27/102H03K17/735H04Q3/52H01L27/04H01L29/72H01L29/747
    • H03K17/735H01L21/761H01L27/1027H04Q3/521H01L27/0203
    • The switching matrix with a plurality of individual lateral type PNPN type switching elements is disposed on a one chip silicon. The chip includes a double layered substrate having a thin P type layer with low impurity concentration epitaxial-grown on a P.sup.+ type layer with high impurity concentration and an N type layer with low impurity concentration epitaxially grown on the P type layer. The substrate has a low resistance. An N.sup.+ type buried layer with high impurity concentration is diffused into the junction between the P type layer and the N type layer at the location where the switching element is to be disposed. The switching element is formed in the N type layer right above the N.sup.+ type buried layer. P.sup.+ type isolation region with high impurity concentration is diffused into the N type layer, not contacting the N.sup.+ type buried layer but the substrate P type layer and enclosing the N type gate region of the switching element. At this time, between adjacent P.sup.+ type isolation regions is formed a high resistive separation region of the N type layer. With such a construction, the low resistive P/P.sup.+ type double layered substrate and the high resistive N separation layer cooperate to remarkably reduce the signal crosstalk between switching elements.
    • 具有多个单独横向型PNPN型开关元件的开关矩阵设置在单芯片硅上。 该芯片包括具有在P型层上外延生长的具有高杂质浓度的P +型层外延生长的低杂质浓度的低杂质浓度的薄P型层的双层基板和在P型层上外延生长的杂质浓度低的N型层。 该基片具有低电阻。 具有高杂质浓度的N +型掩埋层在开关元件设置位置扩散到P型层和N型层之间的结。 开关元件形成在N +型掩埋层正上方的N型层中。 具有高杂质浓度的P +型隔离区扩散到N型层中,不与N +型掩埋层而是接触衬底P型层并且包围开关元件的N型栅极区。 此时,在相邻的P +型隔离区之间形成N型层的高电阻分离区域。 通过这样的结构,低电阻P / P +型双层基板和高电阻N分离层协调显着地减少开关元件之间的信号串扰。