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    • 1. 发明专利
    • Incense stick stand
    • 敏捷贴纸架
    • JP2005021549A
    • 2005-01-27
    • JP2003270022
    • 2003-07-01
    • Masaki Kojima正樹 小島
    • KOJIMA MASAKI
    • A47G33/00
    • PROBLEM TO BE SOLVED: To provide an incense stick stand remarkably improved in safety by preventing incense sticks from falling outside.
      SOLUTION: The incense stick stand 10 for holding slender rod-shaped incense sticks S comprises a catch pan 30 and an incense holder 40 provided on the catch pan 30 for supporting the incense sticks S sideways above the same. The incense holder 40 may be composed of a base 41 and a holding body 42 to be detachably attached onto the base 41 for holding the incense sticks S above the same. The catch pan 30 may comprise on the outer edge thereof high and low walls 51 and 52 respectively higher and lower than the incense sticks S to be supported above the same, and a lid 60 may be selectively placed on either of them.
      COPYRIGHT: (C)2005,JPO&NCIPI
    • 要解决的问题:通过防止香棒脱落而提供通过安全性提高的香棒架。

      解决方案:用于保持细长的棒状香棒S的香棒架10包括设置在捕捉盘30上的捕获盘30和香炉支架40,用于将香棒S侧面地支撑在其上方。 香料支架40可以由底座41和保持体42构成,以可拆卸地安装在基座41上,用于将香棒S保持在其上方。 捕获盘30可以在其外边缘上包括分别高于和低于要支撑在其上的香棒S的高低壁51和52,并且盖60可以选择性地放置在其中任一个上。 版权所有(C)2005,JPO&NCIPI

    • 6. 发明申请
    • SEMICONDUCTOR DEVICE
    • 半导体器件
    • US20090002055A1
    • 2009-01-01
    • US12146863
    • 2008-06-26
    • Masaki KOJIMA
    • Masaki KOJIMA
    • H03K17/687
    • H03K17/0822H03K17/063H03K2017/0806
    • A switching transistor has its drain and source respectively connected to a gate and a source of an output transistor for supplying output current to a load, and its gate connected to an internal grounding wire GW to be connected to a grounding terminal GND. A resistance element R1 connects the gate to the source of the switching transistor. When a voltage not smaller than a predetermined value is generated across the resistance element R1 at turn-on, due to a parasitic capacitance existing between a power supply terminal. Vcc and the internal grounding wire GW, the switching transistor can be turned on to turn off the output transistor.
    • 开关晶体管的漏极和源极分别连接到栅极和用于向负载提供输出电流的输出晶体管的源极,并且其栅极连接到内部接地线GW以连接到接地端子GND。 电阻元件R1将栅极连接到开关晶体管的源极。 由于存在于电源端子之间的寄生电容,因此在导通时跨越电阻元件R1产生不小于预定值的电压。 Vcc和内部接地线GW,开关晶体管可以导通以关闭输出晶体管。
    • 9. 发明授权
    • Semiconductor device
    • 半导体器件
    • US07924084B2
    • 2011-04-12
    • US12146863
    • 2008-06-26
    • Masaki Kojima
    • Masaki Kojima
    • H03K17/687
    • H03K17/0822H03K17/063H03K2017/0806
    • A switching transistor has its drain and source respectively connected to a gate and a source of an output transistor for supplying output current to a load, and its gate connected to an internal grounding wire GW to be connected to a grounding terminal GND. A resistance element R1 connects the gate to the source of the switching transistor. When a voltage not smaller than a predetermined value is generated across the resistance element R1 at turn-on, due to a parasitic capacitance existing between a power supply terminal. Vcc and the internal grounding wire GW, the switching transistor can be turned on to turn off the output transistor.
    • 开关晶体管的漏极和源极分别连接到栅极和输出晶体管的源极,用于向负载提供输出电流,并且其栅极连接到内部接地线GW以连接到接地端子GND。 电阻元件R1将栅极连接到开关晶体管的源极。 由于存在于电源端子之间的寄生电容,因此在导通时跨越电阻元件R1产生不小于预定值的电压。 Vcc和内部接地线GW,开关晶体管可以导通以关闭输出晶体管。
    • 10. 发明申请
    • Semiconductor device with overcurrent protection circuit
    • 半导体器件带过流保护电路
    • US20090284885A1
    • 2009-11-19
    • US12453210
    • 2009-05-01
    • Masaki Kojima
    • Masaki Kojima
    • H02H9/02
    • H03K17/0822H03K17/145
    • A semiconductor device 1 includes an output MOS transistor M2, a sense MOS transistor M3, a voltage conversion circuit 20 that converts a sense current of the sense MOS transistor M3 into a sense voltage, and control MOS transistor M10 having a gate and a source which receive the sense voltage therebetween and a drain connected to a gate of the output MOS transistor M2. The voltage conversion circuit 20 includes a first MOS transistor M21 diode-connected and a second MOS transistor M22 connected in series to the first transistor M21. A gate of the second transistor M22 is connected to a node between a gate control circuit 6 and a resistor R5 which is connected to the gate of the output MOS transistor M2. A variation in threshold voltage caused by characteristic variation of the control MOS transistor M10 causes a variation in output current limiting value, but the threshold voltage of the first MOS transistor M21 diode-connected varies similarly, whereby the variation in threshold voltage caused by characteristic variation of the control MOS transistor M10 is cancelled. As a result, the variation in output current limiting value is suppressed.
    • 半导体器件1包括输出MOS晶体管M2,感测MOS晶体管M3,将感测MOS晶体管M3的感测电流转换为感测电压的电压转换电路20以及具有栅极和源极的控制MOS晶体管M10, 接收它们之间的感测电压和连接到输出MOS晶体管M2的栅极的漏极。 电压转换电路20包括与第一晶体管M21串联连接的二极管连接的第一MOS晶体管M21和第二MOS晶体管M22。 第二晶体管M22的栅极连接到栅极控制电路6和连接到输出MOS晶体管M2的栅极的电阻器R5之间的节点。 由控制MOS晶体管M10的特性变化引起的阈值电压的变化引起输出电流限制值的变化,但是二极管连接的第一MOS晶体管M21的阈值电压变化相似,由此由特性变化引起的阈值电压的变化 的控制MOS晶体管M10被取消。 结果,抑制了输出电流限制值的变化。