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热词
    • 1. 发明授权
    • Semiconductor device and its testing method
    • 半导体器件及其测试方法
    • US08346499B2
    • 2013-01-01
    • US12883825
    • 2010-09-16
    • Tadayuki InamuraMasahiro Tozuka
    • Tadayuki InamuraMasahiro Tozuka
    • G01R29/00
    • G01R31/3008
    • A semiconductor device 100 including an internal circuit 4 that operates based on an input pattern includes a clock driver 25 that generates an internal clock 7 based on a generated clock 6, a counter 23 that generates count data 28 by counting the generated clock 6, a nonvolatile storage device 22 that stores storage data 27 used in an IDDQ test, a comparator 24 that stops the generation of the internal clock 7 by the clock driver 25 when the count data 28 and the storage data 27 match each other, and a pseudo random number generation circuit 3 that supplies a pseudo random number 8 to the internal circuit 4 in synchronization with the internal clock 7.
    • 包括基于输入图案操作的内部电路4的半导体器件100包括基于生成的时钟6生成内部时钟7的时钟驱动器25,通过对生成的时钟6进行计数来生成计数数据28的计数器23, 存储在IDDQ测试中使用的存储数据27的非易失性存储装置22,当计数数据28和存储数据27相互匹配时停止由时钟驱动器25产生内部时钟7的比较器24以及伪随机 数字产生电路3,与内部时钟7同步地向内部电路4提供伪随机数8。
    • 2. 发明申请
    • SEMICONDUCTOR DEVICE AND ITS TESTING METHOD
    • 半导体器件及其测试方法
    • US20110071786A1
    • 2011-03-24
    • US12883825
    • 2010-09-16
    • Tadayuki INAMURAMasahiro Tozuka
    • Tadayuki INAMURAMasahiro Tozuka
    • G01R31/14
    • G01R31/3008
    • A semiconductor device 100 including an internal circuit 4 that operates based on an input pattern includes a clock driver 25 that generates an internal clock 7 based on a generated clock 6, a counter 23 that generates count data 28 by counting the generated clock 6, a nonvolatile storage device 22 that stores storage data 27 used in an IDDQ test, a comparator 24 that stops the generation of the internal clock 7 by the clock driver 25 when the count data 28 and the storage data 27 match each other, and a pseudo random number generation circuit 3 that supplies a pseudo random number 8 to the internal circuit 4 in synchronization with the internal clock 7.
    • 包括基于输入图案操作的内部电路4的半导体器件100包括基于生成的时钟6生成内部时钟7的时钟驱动器25,通过对生成的时钟6进行计数来生成计数数据28的计数器23, 存储在IDDQ测试中使用的存储数据27的非易失性存储装置22,当计数数据28和存储数据27相互匹配时停止由时钟驱动器25产生内部时钟7的比较器24以及伪随机 数字产生电路3,与内部时钟7同步地向内部电路4提供伪随机数8。