专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5369046A Method for forming a gate array base cell 失效
标题翻译：形成栅阵列基电池的方法
公开(公告)号：US5369046A
公开(公告)日：1994-11-29
申请号：US968213
申请日：1992-10-29
申请人： Masahashi Hashimoto , Shivaling S. Mahant-Shetti
发明人： Masahashi Hashimoto , Shivaling S. Mahant-Shetti
IPC分类号： H01L21/82 , H01L21/8238 , H01L27/092 , H01L27/118 , H01C21/265 , H01L21/28
CPC分类号： H01L27/11807 , Y10S257/903
摘要： A semiconductor 110 device includes an array of like base cells wherein each base cell includes at least one source 132 and at least one drain 130 region formed in a semiconductor substrate. At least one gate 126 is formed over and insulated from a channel region 118 which separates the source 132 and drain 130 regions. An insulating layer 190 overlies the structure. A plurality of contacts are formed in the insulating layer in a plurality of substantially parallel, evenly spaced grid lines G1-G5. In addition, at least one additional contact 150 formed between two adjacent ones G2 and G3 of the substantially parallel grid lines is formed. A plurality of interconnect lines 142 and 144 are formed over the insulating layer such that each contact is connected to at least one of the interconnect lines. Modifications, variations, circuit configurations and an illustrative fabrication method are also disclosed.
摘要翻译：半导体110器件包括类似的基本单元的阵列，其中每个基极单元包括形成在半导体衬底中的至少一个源极132和至少一个漏极130区域。至少一个栅极126形成在分离源极132和漏极130区域的沟道区域118的上方并与其绝缘。绝缘层190覆盖在结构上。多个触点形成在绝缘层中的多个基本上平行的均匀间隔的格栅线G1-G5中。此外，形成在基本上平行的栅格线的两个相邻的G2和G3之间形成的至少一个附加触点150。多个互连线142和144形成在绝缘层上，使得每个触点连接到互连线中的至少一个。还公开了修改，变型，电路配置和说明性制造方法。

IPRDB

热门服务

关于我们

友情链接

联系方式