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1. 发明专利

JP2009114827A Device for preventing edge of toilet bowl from splashing with urine 审中-公开
标题翻译：用于防止厕所边缘从尿液排出的装置
公开(公告)号：JP2009114827A
公开(公告)日：2009-05-28
申请号：JP2007312846
申请日：2007-11-05
申请人： Masaaki Yashiro , 正昭八城
发明人： YASHIRO MASAAKI
IPC分类号： E03D9/00 , A47K17/02
摘要： PROBLEM TO BE SOLVED: To solve a problem that, when a man discharges urine into a Western-style toilet in an erection state on awakening, the urine scatters on an edge of the toilet bowl, which has made the family he lives with feel unpleasant.
SOLUTION: The device prevents an edge of a toilet bowl from splashing when discharging urine in a standing position at the Western-style toilet. Using the invention, one can discharge urine pleasantly.
COPYRIGHT: (C)2009,JPO&INPIT
摘要翻译：要解决的问题：为了解决一个问题，当一个人在醒来时将尿液排放到建立状态的西式厕所中时，尿液会排泄在马桶的边缘，这使得他所住的家庭感觉不舒服
解决方案：在西式马桶的立场排放尿液时，该装置可防止马桶的边缘飞溅。使用本发明，可以令人愉快地排尿。版权所有（C）2009，JPO＆INPIT

2. 发明授权

US5057887A High density dynamic RAM cell 失效
标题翻译：高密度动态RAM单元
公开(公告)号：US5057887A
公开(公告)日：1991-10-15
申请号：US366801
申请日：1989-06-14
申请人： Masaaki Yashiro , Shigeki Morinaga , Clarence W. Teng
发明人： Masaaki Yashiro , Shigeki Morinaga , Clarence W. Teng
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/06 , H01L29/40
CPC分类号： H01L27/10829 , Y10S257/90
摘要： The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area. A self-aligned process is used to form the source (14) and drain (12) for the pass gate transistor and automatic connection between the source of the transistor and the buried doping layer is made by the buried N+ layer. A sidewall silicon nitride passivation filament (38) is formed to protect the sidewalls of the interlevel insulator region between the first (30) and second (3-3, 3-4) polycrystalline silicon layers.

3. 发明授权

US5364812A High density dynamic RAM cell 失效
标题翻译：高密度动态RAM单元
公开(公告)号：US5364812A
公开(公告)日：1994-11-15
申请号：US86524
申请日：1993-07-01
申请人： Masaaki Yashiro , Shigeki Morinaga , Clarence W. Teng
发明人： Masaaki Yashiro , Shigeki Morinaga , Clarence W. Teng
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L21/70
CPC分类号： H01L27/10829 , Y10S257/90
摘要： The described embodiments of the present invention provide a memory cell and method for fabricating that memory cell and memory array including the cell. The memory cell is a trench capacitor type having a transistor (1-1-2) formed on the surface of a major face of a substrate (16) and having a capacitor (2-1-2) formed in the substrate around the periphery of a trench. The capacitor and transistor are connected by a buried, heavily doped region (26) having the opposite conductivity type from the substrate. A doped storage area (24) having the same doping type as the buried doped region surrounds the trench. A field plate (30) is formed in the trench separated from the storage region by a dielectric layer (32). The field plate extends onto the isolation areas between memory cells thus providing isolation between cells using a minimum of surface area. A self-aligned process is used to form the source (14) and drain (12) for the pass gate transistor and automatic connection between the source of the transistor and the buried doping layer is made by the buried N+ layer. A sidewall silicon nitride passivation filament (38) is formed to protect the sidewalls of the interlevel insulator region between the first (30) and second (3-3, 3-4) polycrystalline silicon layers.
摘要翻译：本发明的所描述的实施例提供了一种用于制造包括该单元的存储单元和存储器阵列的存储单元和方法。存储单元是具有形成在基板（16）的主面的表面上的晶体管（1-1-2）的沟槽电容器型，并且在周围形成有基板的电容器（2-1-2）的沟渠电容器和晶体管通过与衬底具有相反导电类型的掩埋的重掺杂区域（26）连接。具有与掩埋掺杂区相同的掺杂类型的掺杂存储区（24）围绕沟槽。通过电介质层（32），在与沟槽区分开的沟槽中形成场板（30）。场板延伸到存储单元之间的隔离区域，从而使用最小的表面积来提供电池之间的隔离。自对准工艺用于形成栅极晶体管的源极（14）和漏极（12），晶体管的源极和掩埋掺杂层之间的自动连接由掩埋的N +层制成。形成侧壁氮化硅钝化丝（38）以保护第一（30）和第二（3-3,3-4）多晶硅层之间的层间绝缘体区域的侧壁。

4. 发明授权

US4978634A Method of making trench DRAM cell with stacked capacitor and buried lateral contact 失效
标题翻译：制造具有堆叠电容器和埋入侧面接触的沟槽DRAM单元的方法
公开(公告)号：US4978634A
公开(公告)日：1990-12-18
申请号：US385327
申请日：1989-07-25
申请人： Bing-Whey Shen , Masaaki Yashiro , Randy McKee , Gishi Chung , Kiyoshi Shirai , Clarence Teng , Donald J. Coleman, Jr.
发明人： Bing-Whey Shen , Masaaki Yashiro , Randy McKee , Gishi Chung , Kiyoshi Shirai , Clarence Teng , Donald J. Coleman, Jr.
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10861
摘要： The described embodiments of the present invention provide DRAM cells, structures and manufaturing methods. In a first embodiment, a DRAM cell with a trench capacitor having a first plate formed as a diffusion on the outside surface of a trench formed in the substrate and a second plate having a conductive region formed inside the trench is fabricated. The transfer transistor is formed using a field plate isolation structure which includes a self-aligned moat area for the transfer transistor. The moat area slightly overlaps the capacitor area and allows for increased misalignment tolerance thus foregoing the requirement for misalignment tolerances built into the layout of the DRAM cell. The field plate itself is etched so that it has sloped sidewalls to avoid the formation of conductive filaments from subsequent conductive layers formed on the integrated circuit. The use of a self-aligned bitline contact between two memory cells allows for the elimination of alignment tolerances between the bitline contact and the gates of the transfer transistors of the memory cells.
摘要翻译：本发明的所述实施例提供了DRAM单元，结构和制造方法。在第一实施例中，制造具有沟槽电容器的DRAM单元，该沟槽电容器具有形成为在衬底中形成的沟槽的外表面上的扩散的第一板，以及形成在沟槽内部的导电区域的第二板。转移晶体管使用场板隔离结构形成，该场板隔离结构包括用于转移晶体管的自对准的沟槽区域。护城河区域与电容器区域稍微重叠，并且允许增加的不对准公差，从而对DRAM单元的布局中内置的未对准公差的要求进行了前提。场板本身被蚀刻，使得其具有倾斜的侧壁，以避免由形成在集成电路上的后续导电层形成导电细丝。使用两个存储单元之间的自对准位线接触允许消除位线接触和存储器单元的传输晶体管的栅极之间的对准公差。

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