专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5126805A Junction field effect transistor with SiGe contact regions 失效
标题翻译：具有SiGe接触区域的结型场效应晶体管
公开(公告)号：US5126805A
公开(公告)日：1992-06-30
申请号：US593145
申请日：1990-10-05
申请人： Emel S. Bulat , Marvin J. Tabasky
发明人： Emel S. Bulat , Marvin J. Tabasky
IPC分类号： H01L21/285 , H01L21/337 , H01L29/45 , H01L29/772
CPC分类号： H01L29/66901 , H01L21/28512 , H01L29/452 , H01L29/7722
摘要： A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions. The germanium is intermixed with the underlying silicon to form a germanium-silicon composite. A rapid thermal anneal is performed to recrystallize the germanium-silicon composite. Alternatively, a single crystal epitaxial layer may be deposited on the silicon. Conventional metallization procedures are employed to produce ohmic source and gate contact members to the germanium-silicon composite or the epitaxial germanium of the source and gate regions. By virtue of the reduced bandgap provided by the presence of the germanium, the contact resistance of the device is reduced.
摘要翻译：结型场效应晶体管，特别是静态感应晶体管。在金属化之前，将薄的锗层放置在源极和栅极区域的暴露的硅上。将锗与下面的硅混合以形成锗 - 硅复合材料。进行快速热退火以使锗 - 硅复合材料重结晶。或者，可以在硅上沉积单晶外延层。采用传统的金属化方法来生产欧姆源极和栅极接触元件到锗硅复合物或源极和栅极区域的外延锗。由于由锗的存在而提供的带隙减小，器件的接触电阻降低。

2. 发明授权

US4631806A Method of producing integrated circuit structures 失效
标题翻译：集成电路结构的制造方法
公开(公告)号：US4631806A
公开(公告)日：1986-12-30
申请号：US736881
申请日：1985-05-22
申请人： Paul E. Poppert , Marvin J. Tabasky , Eugene O. Degenkolb
发明人： Paul E. Poppert , Marvin J. Tabasky , Eugene O. Degenkolb
IPC分类号： H01L21/027 , H01L21/768 , H01L21/28 , H01L21/312 , H01L21/88
CPC分类号： H01L21/0272 , H01L21/7688 , Y10S148/02 , Y10S148/10 , Y10S148/106
摘要： Method of producing two-layer metal interconnections in a semiconductor integrated circuit structure coated with silicon dioxide. Masking material is deposited on the silicon dioxide. Openings are formed in the masking material and then in the silicon dioxide to expose contact areas on the integrated circuit structure. A first metal, tungsten, is deposited on the masking material and on the contact areas exposed at the openings. The masking material and the overlying tungsten are stripped off leaving tungsten only on the contact areas. A second metal, aluminum, is deposited over the silicon dioxide and the tungsten on the contact areas. Aluminum is selectively removed to form a pattern of conductive members of tungsten-aluminum on the contact areas and of aluminum over the silicon dioxide.
摘要翻译：在涂覆有二氧化硅的半导体集成电路结构中制造两层金属互连的方法。掩蔽材料沉积在二氧化硅上。在掩模材料中形成开口，然后形成在二氧化硅中以露出集成电路结构上的接触区域。第一金属钨沉积在掩模材料上和暴露在开口处的接触区域上。剥离掩模材料和上覆的钨，仅在接触区域留下钨。第二金属铝沉积在接触区域上的二氧化硅和钨上。选择性地去除铝以在接触区域上形成钨 - 铝的导电构件图案，并在二氧化硅上形成铝。

3. 发明授权

US4693783A Method of producing interconnections in a semiconductor integrated circuit structure 失效
标题翻译：在半导体集成电路结构中制造互连的方法
公开(公告)号：US4693783A
公开(公告)日：1987-09-15
申请号：US687705
申请日：1984-12-31
申请人： Paul E. Poppert , Marvin J. Tabasky
发明人： Paul E. Poppert , Marvin J. Tabasky
IPC分类号： H01L21/768 , B23P15/00
CPC分类号： H01L21/76877
摘要： Method of producing metal interconnections in a semiconductor integrated circuit structure of a body of silicon coated with silicon dioxide having openings therein exposing contact regions to underlying silicon. A thick layer of an insulating or dielectric material, for example, polymide, is deposited on the body. Grooves in the pattern of the desired interconnections are etched through the thick insulating layer to the underlying silicon dioxide and contact regions. Metal is deposited to fill the grooves and cover the thick layer of insulating material. Excess metal is removed to form a planar surface exposing the surface of the thick insulating layer with the grooves containing metal to provide electrical connections between contact regions.
摘要翻译：在用二氧化硅涂覆的硅体的半导体集成电路结构中制造金属互连的方法，其具有开口，其将接触区域暴露于下面的硅。绝缘或电介质材料（例如聚酰亚胺）的厚层沉积在主体上。以期望的互连图案的凹槽通过厚的绝缘层蚀刻到下面的二氧化硅和接触区域。沉积金属以填充凹槽并覆盖厚的绝缘材料层。去除多余的金属以形成暴露厚绝缘层的表面的平坦表面，其中凹槽包含金属以提供接触区域之间的电连接。

4. 发明授权

US4633290A Monolithic CMOS integrated circuit structure with isolation grooves 失效
标题翻译：具有隔离沟槽的单片CMOS集成电路结构
公开(公告)号：US4633290A
公开(公告)日：1986-12-30
申请号：US834713
申请日：1986-02-28
申请人： Paul E. Poppert , Marvin J. Tabasky , Eugene O. Degenkolb
发明人： Paul E. Poppert , Marvin J. Tabasky , Eugene O. Degenkolb
IPC分类号： H01L21/762 , H01L21/763 , H01L21/8238 , H01L27/092 , H01L27/02 , H01L27/04 , H01L29/04 , H01L29/06
CPC分类号： H01L21/823878 , H01L21/76202 , H01L21/76229 , H01L21/76232 , H01L21/763 , H01L27/0928
摘要： Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.
摘要翻译：通过在硅体中形成N型和P型导电性部分来形成用于制造CMOS FET的衬底的方法。在N和P型部分刻蚀凹槽，以产生由凹槽包围的N型和P型部分。槽的表面被氧化，槽被多晶硅填充，并且多晶硅的暴露表面被氧化以形成围绕扇形并将它们电隔离的屏障。在N和P型扇区外部的区域中刻蚀浅沟槽，并且沟槽填充有二氧化硅区域。在两个扇区中制造一对互补FET，并且它们之间的金属互连覆盖着二氧化硅区域的一部分。

5. 发明授权

US4593459A Monolithic integrated circuit structure and method of fabrication 失效
标题翻译：整体集成电路结构及其制造方法
公开(公告)号：US4593459A
公开(公告)日：1986-06-10
申请号：US687409
申请日：1984-12-28
申请人： Paul E. Poppert , Marvin J. Tabasky , Eugene O. Degenkolb
发明人： Paul E. Poppert , Marvin J. Tabasky , Eugene O. Degenkolb
IPC分类号： H01L21/762 , H01L21/763 , H01L21/8238 , H01L27/092 , H01L21/76 , H01L21/82
CPC分类号： H01L21/76232 , H01L21/76202 , H01L21/76229 , H01L21/763 , H01L21/823878 , H01L27/0928 , Y10S148/07 , Y10S148/085 , Y10S148/086
摘要： Method of forming a substrate for fabricating CMOS FET's by forming sections of N and P-type conductivity in a body of silicon. Grooves are etched in the N and P-type sections to produce N and P-type sectors encircled by grooves. The surfaces of the grooves are oxidized, the grooves are filled with polycrystalline silicon, and exposed surfaces of the polycrystalline silicon are oxidized to form barriers which encircle the sectors and electrically isolate them. Shallow trenches are etched in regions of the body outside the N and P-type sectors and the trenches are filled with regions of silicon dioxide. A pair of complementary FET's are fabricated in the two sectors and a metal interconnection between them overlies a portion of a region of silicon dioxide.
摘要翻译：通过在硅体中形成N型和P型导电性部分来形成用于制造CMOS FET的衬底的方法。在N和P型部分刻蚀凹槽，以产生由凹槽包围的N型和P型部分。槽的表面被氧化，槽被多晶硅填充，并且多晶硅的暴露表面被氧化以形成围绕扇形并将它们电隔离的屏障。在N和P型扇区外部的区域中刻蚀浅沟槽，并且沟槽填充有二氧化硅区域。在两个扇区中制造一对互补FET，并且它们之间的金属互连覆盖着二氧化硅区域的一部分。

6. 发明授权

US5163108A Method and device for passive alignment of diode lasers and optical fibers 失效
标题翻译：用于二极管激光器和光纤的无源对准的方法和装置
公开(公告)号：US5163108A
公开(公告)日：1992-11-10
申请号：US739587
申请日：1991-08-02
申请人： Craig A. Armiento , Chirravuri Jagannath , Marvin J. Tabasky , Thomas W. Fitzgerald , Harry F. Lockwood , Paul O. Haugsjaa , Mark A. Rothman , Vincent J. Barry , Margaret B. Stern
发明人： Craig A. Armiento , Chirravuri Jagannath , Marvin J. Tabasky , Thomas W. Fitzgerald , Harry F. Lockwood , Paul O. Haugsjaa , Mark A. Rothman , Vincent J. Barry , Margaret B. Stern
IPC分类号： G02B6/42 , H01S5/02 , H01S5/40
CPC分类号： G02B6/423 , G02B6/4249 , H01S5/02 , H01S5/4025 , G02B6/4238
摘要： A method of passively aligning optical receiving elements such as fibers to the active elements of a light generating chip includes the steps of forming two front and one side pedestal structures on the surface of a substrate body, defining a vertical sidewall of the chip to form a mating channel having an edge at a predetermined distance from the first active element, mounting the chip epi-side down on the substrate surface, and positioned the fibers in fiber-receiving channels so that a center line of each fiber is aligned to a center line of a respective active element. When mounted, the front face of the chip is abutting the contact surfaces of the two front pedestals, and the defined sidewall of the mating channel is abutting the contact surface of the side pedestal. The passive alignment procedure is also effective in aligning a single fiber to a single active element.
摘要翻译：将诸如光纤的光接收元件被动地对准发光芯片的有源元件的方法包括以下步骤：在衬底主体的表面上形成两个前和底侧基座结构，限定芯片的垂直侧壁以形成配合通道具有距离第一有源元件预定距离的边缘，将芯片外延安装在基板表面上，并将光纤定位在光纤接收通道中，使得每个光纤的中心线与中心线对准的相应活性元素。当安装时，芯片的前表面抵靠两个前基座的接触表面，并且配合通道的限定侧壁邻接侧基座的接触表面。被动对准程序在将单个光纤对准单个有源元件方面也是有效的。

7. 发明授权

US5077878A Method and device for passive alignment of diode lasers and optical fibers 失效
标题翻译：用于二极管激光和光纤的被动对准的方法和装置
公开(公告)号：US5077878A
公开(公告)日：1992-01-07
申请号：US551219
申请日：1990-07-11
申请人： Craig A. Armiento , Chirravuri Jagannath , Marvin J. Tabasky , Thomas W. Fitzgerald , Harry F. Lockwood , Paul O. Haugsjaa , Mark A. Rothman , Vincent J. Barry , Margaret B. Stern
发明人： Craig A. Armiento , Chirravuri Jagannath , Marvin J. Tabasky , Thomas W. Fitzgerald , Harry F. Lockwood , Paul O. Haugsjaa , Mark A. Rothman , Vincent J. Barry , Margaret B. Stern
IPC分类号： H01S5/00 , G02B6/42 , H01S5/02 , H01S5/026 , H01S5/40
CPC分类号： H01S5/4025 , G02B6/423 , G02B6/4249 , H01S5/02 , G02B6/4238 , Y10S148/095 , Y10T29/413
摘要： A method of passively aligning optical receiving elements such as fibers to the active elements of a light generating chip includes the steps of forming two front and one side pedestal structures on the surface of a substrate body, defining a vertical sidewall of the chip to form a mating channel having an edge at a predetermined distance from the first active element, mounting the chip epi-side down on the substrate surface, and positioning the fibers in fiber-receiving channels to that a center line of each fiber is aligned to a center line of a respective active element. When mounted, the front face of the chip is abutting the contact surfaces of the two front pedestals, and the defined sidewall of the mating channel is abutting the contact surface of the side pedestal. The passive alignment procedure is also effective in aligning a single fiber to a single active element.

8. 发明授权

US4983536A Method of fabricating junction field effect transistor 失效
标题翻译：连接场效应晶体管的制造方法
公开(公告)号：US4983536A
公开(公告)日：1991-01-08
申请号：US440930
申请日：1989-11-24
申请人： Emel S. Bulat , Marvin J. Tabasky
发明人： Emel S. Bulat , Marvin J. Tabasky
IPC分类号： H01L29/808 , H01L21/337 , H01L29/45 , H01L29/772
CPC分类号： H01L29/66901 , H01L29/452 , H01L29/7722 , Y10S148/059
摘要： A junction field effect transistor, specifically a static induction transistor. Prior to metallization a thin layer of germanium is placed over the exposed silicon of the source and gate regions. The germanium is intermixed with the underlying silicon to form a germanium-silicon composite. A rapid thermal anneal is performed to recrystallize the germanium-silicon composite. Alternatively, a single crystal epitaxial layer may be deposited on the silicon. Conventional metallization procedures are employed to produce ohmic source and gate contact members to the germanium-silicon composite or the epitaxial germanium of the source and gate regions. By virtue of the reduced bandgap provided by the presence of the germanium, the contact resistance of the device is reduced.

9. 发明授权

US5045346A Method of depositing fluorinated silicon nitride 失效
标题翻译：沉积氟化氮化硅的方法
公开(公告)号：US5045346A
公开(公告)日：1991-09-03
申请号：US560688
申请日：1990-07-31
申请人： Marvin J. Tabasky , Bruce Tweed
发明人： Marvin J. Tabasky , Bruce Tweed
IPC分类号： C23C16/34 , C23C16/509 , H01L21/318
CPC分类号： C23C16/509 , C23C16/345
摘要： Method of forming a fluorinated silicon nitride film on a semiconductor substrate by first forming a coating of ammonium hexafluorosilicate on the electrode of a plasma reactor to serve as a source of fluorine during the silicon nitride deposition procedure. The ammonium hexafluorosilicate coating is formed by generating a plasma of carbon tetrafluoride and oxygen within the reactor, then a plasma of nitrogen, followed by a plasma of silane and helium with nitrogen. The substrate is then placed in the reactor and a plasma employing silane and helium together with nitrogen is generated at low RF frequency to produce a fluorinated silicon nitride film on the substrate.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式