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1. 发明授权

US06268630B1 Silicon-on-insulator field effect transistor with improved body ties for rad-hard applications 有权
标题翻译：绝缘体上的场效应晶体管，具有改进的体态连接，适用于辐射硬件应用
公开(公告)号：US06268630B1
公开(公告)日：2001-07-31
申请号：US09270374
申请日：1999-03-16
申请人： James R. Schwank , Marty R. Shaneyfelt , Bruce L. Draper , Paul E. Dodd
发明人： James R. Schwank , Marty R. Shaneyfelt , Bruce L. Draper , Paul E. Dodd
IPC分类号： H01L2900
CPC分类号： H01L27/1203 , H01L21/84 , H01L29/78609 , H01L29/78618
摘要： A silicon-on-insulator (SOI) field-effect transistor (FET) and a method for making the same are disclosed. The SOI FET is characterized by a source which extends only partially (e.g. about half-way) through the active layer wherein the transistor is formed. Additionally, a minimal-area body tie contact is provided with a short-circuit electrical connection to the source for reducing floating body effects. The body tie contact improves the electrical characteristics of the transistor and also provides an improved single-event-upset (SEU) radiation hardness of the device for terrestrial and space applications. The SOI FET also provides an improvement in total-dose radiation hardness as compared to conventional SOI transistors fabricated without a specially prepared hardened buried oxide layer. Complementary n-channel and p-channel SOI FETs can be fabricated according to the present invention to form integrated circuits (ICs) for commercial and military applications.
摘要翻译：公开了绝缘体上硅（SOI）场效应晶体管（FET）及其制造方法。 SOI FET的特征在于仅通过形成晶体管的有源层部分地（例如，大约一半）延伸的源极。此外，最小面积的身体接合触点提供与源的短路电连接以减少浮体效应。身体接触触点提高了晶体管的电气特性，并且还提供了用于地面和空间应用的器件的改进的单事件镦粗（SEU）辐射硬度。与没有特别制备的硬化掩埋氧化物层制造的常规SOI晶体管相比，SOI FET也提供总剂量辐射硬度的改善。可以根据本发明制造互补的n沟道和p沟道SOI FET，以形成用于商业和军事应用的集成电路（IC）。

2. 发明授权

US5786231A Screening method for selecting semiconductor substrates having defects below a predetermined level in an oxide layer 失效
标题翻译：在氧化物层中选择具有低于预定水平的缺陷的半导体衬底的筛选方法
公开(公告)号：US5786231A
公开(公告)日：1998-07-28
申请号：US567679
申请日：1995-12-05
申请人： William L. Warren , Karel J. R. Vanheusden , James R. Schwank , Daniel M. Fleetwood , Marty R. Shaneyfelt , Peter S. Winokur , Roderick A. B. Devine
发明人： William L. Warren , Karel J. R. Vanheusden , James R. Schwank , Daniel M. Fleetwood , Marty R. Shaneyfelt , Peter S. Winokur , Roderick A. B. Devine
IPC分类号： H01L21/66 , G01R31/26
CPC分类号： H01L22/14 , H01L22/20
摘要： A method for screening or qualifying semiconductor substrates for integrated circuit fabrication. The method comprises the steps of annealing at least one semiconductor substrate at a first temperature in a defect-activating ambient (e.g. hydrogen, forming gas, or ammonia) for sufficient time for activating any defects within on oxide layer of the substrate; measuring a defect-revealing electrical characteristic of at least a portion of the oxide layer for determining a quantity of activated defects therein; and selecting substrates for which the quantity of activated defects is below a predetermined level. The defect-revealing electrical characteristic may be a capacitance-versus-voltage (C-V) characteristic or a current-versus-voltage (I-V) characteristic that is dependent on an electrical charge in the oxide layer generated by the activated defects. Embodiments of the present invention may be applied for screening any type of semiconductor substrate or wafer having an oxide layer formed thereon or therein. This includes silicon-on-insulator substrates formed by a separation by the implantation of oxygen (SIMOX) process or the bond and etch back silicon-on-insulator (BESOI) process, as well as silicon substrates having a thermal oxide layer or a deposited oxide layer.
摘要翻译：一种用于集成电路制造的半导体衬底的筛选或限定方法。该方法包括以下步骤：在缺陷活化环境（例如氢气，形成气体或氨）中的第一温度下退火至少一个半导体衬底足够的时间以激活衬底的氧化物层内的任何缺陷; 测量所述氧化物层的至少一部分的缺陷显露电特性，以确定其中的活化缺陷的量; 以及选择活性缺陷量低于预定水平的衬底。缺陷显露的电气特性可以是取决于由激活的缺陷产生的氧化物层中的电荷的电容 - 电压（C-V）特性或电流 - 电压（I-V）特性。本发明的实施例可以应用于筛选其上形成有氧化层的任何类型的半导体衬底或晶片。这包括通过通过注入氧（SIMOX）工艺分离的绝缘体上硅衬底或绝缘体上的绝缘体（BESOI）工艺的接合和回蚀，以及具有热氧化物层或沉积氧化层。

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