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1. 发明授权

US07627774B2 Redundant manager modules to perform management tasks with respect to an interconnect structure and power supplies 有权
标题翻译：冗余管理器模块，用于执行关于互连结构和电源的管理任务
公开(公告)号：US07627774B2
公开(公告)日：2009-12-01
申请号：US11066024
申请日：2005-02-25
申请人： Kevin A. Egan , Brad O. Underwood , Mark E. Shaw , Mark A. Shaw , Brian M. Johnson , D. Glen Edwards
发明人： Kevin A. Egan , Brad O. Underwood , Mark E. Shaw , Mark A. Shaw , Brian M. Johnson , D. Glen Edwards
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F15/16
摘要： A system comprises plural electronic modules, at least one interconnect structure and plural power supplies. The electronic modules communicate over the interconnect structure. The system further comprises plural redundant manager modules to perform management tasks with respect to the at least one interconnect structure and the power supplies.
摘要翻译：一种系统包括多个电子模块，至少一个互连结构和多个电源。电子模块通过互连结构进行通信。该系统还包括多个冗余管理器模块，用于执行关于至少一个互连结构和电源的管理任务。

2. 发明授权

US07589560B2 Apparatus for configuring I/O signal levels of interfacing logic circuits 有权
标题翻译：用于配置接口逻辑电路的I / O信号电平的装置
公开(公告)号：US07589560B2
公开(公告)日：2009-09-15
申请号：US11583322
申请日：2006-10-19
申请人： David Glen Edwards , Brian Matthew Johnson , Mark A. Shaw , Stuart C. Haden
发明人： David Glen Edwards , Brian Matthew Johnson , Mark A. Shaw , Stuart C. Haden
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/082
CPC分类号： H03K19/017581
摘要： Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.
摘要翻译：用于配置以不同电压电平工作的接口逻辑电路的输入/输出信号电平的装置包括：用于在第一电压电平下操作的逻辑电路; 耦合到所述逻辑电路的用于将不同于所述第一电压电平的第二电压电平的输入/输出信号与所述逻辑电路接口的一组输入/输出门，所述一组门包括用于设置其操作电压电平的端口 ; 以及控制电路，其耦合到端口并由控制信号控制以配置栅极组的操作电压电平以使逻辑电路和接口输入/输出信号电压电平相容。

3. 发明授权

US07719312B2 Apparatus for configuring I/O signal levels of interfacing logic circuits 有权
标题翻译：用于配置接口逻辑电路的I / O信号电平的装置
公开(公告)号：US07719312B2
公开(公告)日：2010-05-18
申请号：US12458204
申请日：2009-07-02
申请人： David Glen Edwards , Brian Matthew Johnson , Mark A. Shaw , Stuart C. Haden
发明人： David Glen Edwards , Brian Matthew Johnson , Mark A. Shaw , Stuart C. Haden
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/082
CPC分类号： H03K19/017581
摘要： Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.
摘要翻译：用于配置以不同电压电平工作的接口逻辑电路的输入/输出信号电平的装置包括：用于在第一电压电平下操作的逻辑电路; 耦合到所述逻辑电路的用于将不同于所述第一电压电平的第二电压电平的输入/输出信号与所述逻辑电路接口的一组输入/输出门，所述一组门包括用于设置其操作电压电平的端口 ; 以及控制电路，其耦合到端口并由控制信号控制以配置栅极组的操作电压电平以使逻辑电路和接口输入/输出信号电压电平相容。

4. 发明授权

US08799700B2 Providing fault-tolerant spread spectrum clock signals in a system 有权
标题翻译：在系统中提供容错扩频时钟信号
公开(公告)号：US08799700B2
公开(公告)日：2014-08-05
申请号：US13379276
申请日：2009-07-31
申请人： Rangaswamy Arumugham , Stuart Haden , Mark A. Shaw
发明人： Rangaswamy Arumugham , Stuart Haden , Mark A. Shaw
IPC分类号： G06F11/00 , G06F1/10 , G06F11/16 , G06F11/20
CPC分类号： G06F11/1604 , G06F1/10 , G06F11/004 , G06F11/20
摘要： To provide fault-tolerant, spread spectrum clock signals, a plurality of processing modules having respective spread spectrum control circuits are provided. Clock signals of redundant clock sources are provided to the plurality of processing modules. Failover control logic selects a corresponding one of the clock signals from the redundant clock sources for use in each of the processing modules. Frequency spreading is applied to the corresponding selected clock signal in each of at least some of the plurality of processing module.
摘要翻译：为了提供容错的扩频时钟信号，提供了具有各自扩频控制电路的多个处理模块。冗余时钟源的时钟信号被提供给多个处理模块。故障转移控制逻辑从冗余时钟源中选择相应的一个时钟信号，以在每个处理模块中使用。在多个处理模块中的至少一些处理模块的每一个中对相应的所选择的时钟信号施加频率扩展。

5. 发明申请

US20120117415A1 PROVIDING FAULT-TOLERANT SPREAD SPECTRUM CLOCK SIGNALS IN A SYSTEM 有权
标题翻译：在系统中提供容错扩展频谱信号
公开(公告)号：US20120117415A1
公开(公告)日：2012-05-10
申请号：US13379276
申请日：2009-07-31
申请人： Rangaswamy Arumugham , Stuart Haden , Mark A. Shaw
发明人： Rangaswamy Arumugham , Stuart Haden , Mark A. Shaw
IPC分类号： G06F1/08
CPC分类号： G06F11/1604 , G06F1/10 , G06F11/004 , G06F11/20
摘要： To provide fault-tolerant, spread spectrum clock signals, a plurality of processing modules having respective spread spectrum control circuits are provided. Clock signals of redundant clock sources are provided to the plurality of processing modules. Failover control logic selects a corresponding one of the clock signals from the redundant clock sources for use in each of the processing modules. Frequency spreading is applied to the corresponding selected clock signal in each of at least some of the plurality of processing module.
摘要翻译：为了提供容错的扩频时钟信号，提供了具有各自扩频控制电路的多个处理模块。冗余时钟源的时钟信号被提供给多个处理模块。故障转移控制逻辑从冗余时钟源中选择相应的一个时钟信号，以便在每个处理模块中使用。在多个处理模块中的至少一些处理模块的每一个中对相应的所选择的时钟信号施加频率扩展。

6. 发明申请

US20090267648A1 Apparatus for configuring I/O signal levels of interfacing logic circuits 有权
公开(公告)号：US20090267648A1
公开(公告)日：2009-10-29
申请号：US12458204
申请日：2009-07-02
申请人： David Glen Edwards , Brian Matthew Johnson , Mark A. Shaw , Stuart C. Haden
发明人： David Glen Edwards , Brian Matthew Johnson , Mark A. Shaw , Stuart C. Haden
IPC分类号： H03K19/0175
CPC分类号： H03K19/017581
摘要： Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.

7. 发明授权

US06888860B2 Low cost optical bench having high thermal conductivity 失效
标题翻译：低成本光学工作台具有高导热性
公开(公告)号：US06888860B2
公开(公告)日：2005-05-03
申请号：US10012144
申请日：2001-12-07
申请人： Mark A. Shaw
发明人： Mark A. Shaw
IPC分类号： G02B6/42 , H01S5/02 , H01S5/022 , H01S5/024 , H01S3/04
CPC分类号： H01S5/02216 , G02B6/4201 , G02B6/4202 , G02B6/4237 , H01S5/02248 , H01S5/02415 , H01S5/02476
摘要： The invention relates with an optical bench for optoelectronic packages comprising a rigid insulating substrate, the substrate having a top surface along which it is defined an optical axis, the substrate comprising: a device region for mounting at least an optoelectronic device in alignment with the optical axis, and a fixing region adjacent to the device region for affixing at least an optical component in alignment with the optical axis. The substrate further comprises a third region provided with metallised tracks, the third region extending over the substrate top surface along at least part of one side of the fixing region in a direction substantially parallel to the optical axis. The invention also relates with an optical bench comprising: a single baseplate having a device region and a fixing region; a welding platform mounted directly on said fixing region; a heat sink mounted directly on said device region; and an optoelectronic device directly mounted on said heat sink.
摘要翻译：本发明涉及一种用于光电子封装的光学平台，其包括刚性绝缘基板，该基板具有沿其定义的光轴的顶表面，该基板包括：用于安装至少一个与该光学元件对准的光电子器件的器件区域以及与装置区域相邻的固定区域，用于至少固定与光轴对准的光学部件。衬底还包括设置有金属化轨道的第三区域，第三区域沿着基本上平行于光轴的方向沿着固定区域的一侧的至少一部分在衬底顶表面上延伸。本发明还涉及一种光学工作台，包括：具有装置区域和固定区域的单个基板; 直接安装在所述固定区上的焊接平台; 直接安装在所述装置区域上的散热片; 以及直接安装在所述散热器上的光电子器件。

8. 发明申请

US20080094106A1 Apparatus for configuring I/O signal levels of interfacing logic circuits 有权
标题翻译：用于配置接口逻辑电路的I / O信号电平的装置
公开(公告)号：US20080094106A1
公开(公告)日：2008-04-24
申请号：US11583322
申请日：2006-10-19
申请人： David Glen Edwards , Brian Matthew Johnson , Mark A. Shaw , Stuart C. Haden
发明人： David Glen Edwards , Brian Matthew Johnson , Mark A. Shaw , Stuart C. Haden
IPC分类号： H03K19/0175
CPC分类号： H03K19/017581
摘要： Apparatus for configuring input/output signal levels of interfacing logic circuits operating at different voltage levels comprises: a logic circuit for operating at a first voltage level; a bank of input/output gates coupled to the logic circuit for interfacing input/output signals at a second voltage level, different from the first voltage level, to the logic circuit, the bank of gates including a port for setting the operational voltage level thereof; and a control circuit coupled to the port and governed by a control signal to configure the operational voltage level of the bank of gates to render the logic circuit and the interfacing input/output signals voltage level compatible.
摘要翻译：用于配置以不同电压电平工作的接口逻辑电路的输入/输出信号电平的装置包括：用于在第一电压电平下操作的逻辑电路; 耦合到所述逻辑电路的用于将不同于所述第一电压电平的第二电压电平的输入/输出信号与所述逻辑电路接口的一组输入/输出门，所述一组门包括用于设置其操作电压电平的端口 ; 以及控制电路，其耦合到端口并由控制信号控制以配置栅极组的操作电压电平以使逻辑电路和接口输入/输出信号电压电平相容。

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