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1. 发明授权

US06247164B1 Configurable hardware system implementing Boolean Satisfiability and method thereof 失效
标题翻译：可配置硬件系统实现布尔满足度及其方法
公开(公告)号：US06247164B1
公开(公告)日：2001-06-12
申请号：US08919282
申请日：1997-08-28
申请人： Pranav Ashar , Sharad Malik , Margaret Martonosi , Peixin Zhong
发明人： Pranav Ashar , Sharad Malik , Margaret Martonosi , Peixin Zhong
IPC分类号： G06F1750
CPC分类号： G06F17/504
摘要： Disclosed is a configurable hardware system and method for implementing instance-specific (per-formula) SAT-solver circuits. A template design is provided for producing these circuits on a per-formula basis. The typical hardware requirements for implementing the invention makes the design amenable to current or next-generation FPGA implementation. Hardware simulations indicate that for many difficult SAT problems, the system according to the invention can offer one to three orders of magnitude speedup over prior art software implementations.
摘要翻译：公开了用于实现实例特定（每公式）SAT解算器电路的可配置硬件系统和方法。提供了一个模板设计，用于在每个公式的基础上产生这些电路。实现本发明的典型硬件要求使得设计适合当前或下一代FPGA实现。硬件模拟表明，对于许多困难的SAT问题，根据本发明的系统可以提供超过现有技术的软件实现一到三个数量级的加速。

2. 发明授权

US08880844B1 Inter-core cooperative TLB prefetchers 有权
标题翻译：核心合作TLB预取器
公开(公告)号：US08880844B1
公开(公告)日：2014-11-04
申请号：US12723012
申请日：2010-03-12
申请人： Abhishek Bhattacharjee , Margaret Martonosi
发明人： Abhishek Bhattacharjee , Margaret Martonosi
IPC分类号： G06F12/04
CPC分类号： G06F12/0215 , G06F12/0862 , G06F12/1009 , G06F12/1027 , G06F2212/1016 , G06F2212/6022 , G06F2212/654 , G06F2212/681 , G06F2212/682 , G06F2212/684
摘要： A chip multiprocessor includes a plurality of cores each having a translation lookaside buffer (TLB) and a prefetch buffer (PB). Each core is configured to determine a TLB miss on the core's TLB for a virtual page address and determine whether or not there is a PB hit on a PB entry in the PB for the virtual page address. If it is determined that there is a PB hit, the PB entry is added to the TLB. If it is determined that there is not a PB hit, the virtual page address is used to perform a page walk to determine a translation entry, the translation entry is added to the TLB and the translation entry is prefetched to each other one of the plurality of cores.
摘要翻译：芯片多处理器包括多个核，每个核具有翻译后备缓冲器（TLB）和预取缓冲器（PB）。每个核心配置为确定虚拟页面地址的核心TLB上的TLB未命中，并确定虚拟页面地址在PB中的PB条目上是否存在PB命中。如果确定存在PB命中，则将PB条目添加到TLB。如果确定没有PB命中，则使用虚拟页面地址来执行页面移动以确定翻译条目，则将翻译条目添加到TLB，并且翻译条目被预取到彼此之一的核心。

3. 发明申请

US20060041769A1 Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay 有权
公开(公告)号：US20060041769A1
公开(公告)日：2006-02-23
申请号：US11245513
申请日：2005-10-07
申请人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
发明人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
IPC分类号： G06F1/30
CPC分类号： G11C5/143 , G11C11/417
摘要： An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased. When a cache line is later accessed after being decayed, a cache miss is incurred and a test is performed to evaluate the cache decay performance by determining if the same cache contents are again accessed (e.g., whether the address associated with a subsequent access is the same address of the previously stored contents). The cache decay interval is then adjusted accordingly.

4. 发明授权

US6038392A Implementation of boolean satisfiability with non-chronological backtracking in reconfigurable hardware 失效
标题翻译：在可重配置硬件中实现具有非时序回溯的布尔可满足性
公开(公告)号：US6038392A
公开(公告)日：2000-03-14
申请号：US85646
申请日：1998-05-27
申请人： Pranav Ashar , Sharad Malik , Margaret Martonosi , Peixin Zhong
发明人： Pranav Ashar , Sharad Malik , Margaret Martonosi , Peixin Zhong
IPC分类号： G06F9/44 , G06F17/10 , G06F17/50 , G06N5/04
CPC分类号： G06F17/5054
摘要： A Boolean SAT solver uses reconfigurable hardware to solve a specific input problem. Each of the plurality of ordered variables has a corresponding one of a plurality of state machines. Each state machine has an implication circuit for its respective variable, and operates in parallel according to an identical state machine. One state machine implements the Davis-Putnam method in hardware and provides improved performance over software by virtue of the parallel checking of direct and transitive implications. Another state machine implements a novel non-chronological backtracking method that takes advantage of the parallel implication checking and avoids the need to maintain or to traverse a GRASP type implication graph in the event of backtracking. The novel non-chronological backtracking provides for setting a blocking variable as a leaf variable and for changing only the value of the leaf variable, but possibly changing both the value and identity of a backtracking variable.
摘要翻译：布尔SAT求解器使用可重构硬件来解决特定的输入问题。多个有序变量中的每一个具有多个状态机中的对应的一个。每个状态机具有用于其各自变量的含义电路，并且根据相同的状态机并行操作。一个状态机通过硬件实现Davis-Putnam方法，并通过并行检查直接和传递的影响，提高了软件性能。另一种状态机实现了一种新颖的非时间回溯方法，其利用并行含义检查的优点，并避免在回溯事件中维护或遍历GRASP类型含义图。新颖的非时间回溯提供将阻塞变量设置为叶变量，并且仅改变叶变量的值，但可能改变回溯变量的值和身份。

5. 发明授权

US06415430B1 Method and apparatus for SAT solver architecture with very low synthesis and layout overhead 有权
标题翻译： SAT求解器架构的方法和设备具有非常低的综合和布局开销
公开(公告)号：US06415430B1
公开(公告)日：2002-07-02
申请号：US09456506
申请日：1999-12-08
申请人： Pranav Ashar , Peixin Zhong , Margaret Martonosi
发明人： Pranav Ashar , Peixin Zhong , Margaret Martonosi
IPC分类号： G06F1750
CPC分类号： G06F17/504 , G06F17/5054
摘要： A method and apparatus for implementing communication between literals and clauses of a Boolean SAT problem through use of a time-multiplexed pipelined bus architecture rather than hardwiring it using on-FPGA routing resources. This technique allows the circuits for different instances of the Boolean SAT problem to be identical except for small local differences. Incremental synthesis and place-and-route effort required for each instance of the Boolean SAT problem becomes negligible compared to the time to actually solve the SAT problem. The time-multiplexing feature allows dynamic addition of clauses into the SAT solver algorithm. The pipeline architecture is highly pipelined with very few long wires and no wires crossing FPGA boundaries, thereby providing high clock speeds.
摘要翻译：一种用于通过使用时间多路复用流水线总线架构而不是使用FPGA路由资源硬连线来实现文本和布尔SAT问题的子句之间的通信的方法和装置。这种技术允许布尔SAT问题的不同实例的电路相同，除了小的局部差异。与实际解决SAT问题的时间相比，布尔SAT问题的每个实例所需的增量合成和布局和布线工作变得可以忽略不计。时间复用功能允许在SAT求解器算法中动态添加子句。流水线架构具有很高的流水线配置，极少的长导线，没有电线穿过FPGA边界，从而提供高的时钟速度。

6. 发明授权

US06324673B1 Method and apparatus for edge-endpoint-based VLSI design rule checking 有权
标题翻译：基于边缘端点的VLSI设计规则检查的方法和装置
公开(公告)号：US06324673B1
公开(公告)日：2001-11-27
申请号：US09321591
申请日：1999-05-28
申请人： Zhen Luo , Margaret Martonosi , Pranav Ashar
发明人： Zhen Luo , Margaret Martonosi , Pranav Ashar
IPC分类号： G06F1750
CPC分类号： G06F17/5081
摘要： The method and apparatus for performing design rule checking on Manhattan structures in VLSI circuit layouts. The method and apparatus provides an edge-endpoint-based technique for checking the geometry and spacing of the VLSI circuit layout. The edge-endpoint-based technique uses a scanline algorithm that detects errors between adjacent structures that do not simultaneously intersect the scanline. The method also provides efficient error compilation. The apparatus allows for the design rules to be changed as the VLSI circuit layout evolves. The apparatus can process the VLSI circuit layout with a single processor, and the apparatus provides for multiple processors to process slices of the VLSI circuit layout, thereby enhancing the speed of the design rule checking over traditional software-only techniques.
摘要翻译：在VLSI电路布局中对曼哈顿结构执行设计规则检查的方法和装置。该方法和装置提供用于检查VLSI电路布局的几何形状和间距的基于边缘端点的技术。基于边缘端点的技术使用扫描线算法来检测不同时与扫描线相交的相邻结构之间的错误。该方法还提供了有效的错误编译。该设备允许随着VLSI电路布局的发展而改变设计规则。该设备可以使用单个处理器来处理VLSI电路布局，并且该设备提供多个处理器来处理VLSI电路布局的片段，从而提高设计规则检查传统的仅软件技术的速度。

7. 发明授权

US07472302B2 Method and apparatus for reducing leakage power in a cache memory using adaptive time-based decay 有权
标题翻译：使用自适应基于时间的衰减来减少高速缓冲存储器中的泄漏功率的方法和装置
公开(公告)号：US07472302B2
公开(公告)日：2008-12-30
申请号：US11245513
申请日：2005-10-07
申请人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
发明人： Zhigang Hu , Stefanos Kaxiras , Margaret Martonosi
IPC分类号： G06F1/32
CPC分类号： G11C5/143 , G11C11/417
摘要： An adaptive cache decay technique is disclosed that removes power from cache lines that have not been accessed for a variable time interval, referred to as the cache line decay interval, assuming that these cache lines are unlikely to be accessed in the future. The decay interval may be increased or decreased for each cache line to increase cache performance or save power, respectively. A default decay interval is initially established for the cache and the default decay interval may then be adjusted for a given cache line based on the performance of the cache line following a cache decay. The cache decay performance is evaluated by determining if a cache line was decayed too quickly. If a cache line is decayed and the same cache contents are again required, then the cache line was decayed too quickly and the cache line decay interval is increased. If a cache line is decayed and the cache line is then accessed to obtain a different cache content, the cache line decay interval can be decreased. When a cache line is later accessed after being decayed, a cache miss is incurred and a test is performed to evaluate the cache decay performance by determining if the same cache contents are again accessed (e.g., whether the address associated with a subsequent access is the same address of the previously stored contents). The cache decay interval is then adjusted accordingly.
摘要翻译：公开了一种自适应高速缓存衰减技术，其假设在将来不太可能访问这些高速缓存线，从而将高速缓存线路的功率从尚未被访问的可变时间间隔（称为高速缓存行衰减间隔）中移除。对于每个高速缓存线，衰减间隔可以增加或减小，以分别提高高速缓存性能或节省功率。初始建立高速缓存的默认衰减间隔，然后可以根据高速缓存衰减之后的高速缓存行的性能，为给定的高速缓存行调整默认衰减间隔。缓存衰减性能通过确定高速缓存行是否衰减太快来进行评估。如果缓存线被衰减并且再次需要相同的高速缓存内容，则高速缓存线被衰减太快，并且高速缓存行衰减间隔增加。如果缓存行被衰减并且然后访问高速缓存行以获得不同的高速缓存内容，则可以减少高速缓存行衰减间隔。当高速缓存行在衰减之后被访问时，产生高速缓存未命中，并且执行测试以通过确定是否再次访问相同的缓存内容来评估高速缓存衰减性能（例如，与后续访问相关联的地址是否为以前存储的内容的相同地址）。然后相应地调整缓存衰减间隔。

8. 发明授权

US06745336B1 System and method of operand value based processor optimization by detecting a condition of pre-determined number of bits and selectively disabling pre-determined bit-fields by clock gating 失效
标题翻译：通过检测预定位数的条件并通过时钟选通选择性地禁用预定位字段的基于操作数值的处理器优化的系统和方法
公开(公告)号：US06745336B1
公开(公告)日：2004-06-01
申请号：US09574793
申请日：2000-05-19
申请人： Margaret Martonosi , David Brooks
发明人： Margaret Martonosi , David Brooks
IPC分类号： G06F132
CPC分类号： G06F9/30025 , G06F1/3203 , G06F1/3237 , G06F1/3243 , G06F1/3287 , G06F7/48 , G06F9/30014 , G06F9/30036 , Y02D10/128 , Y02D10/152 , Y02D10/171
摘要： Circuitry reduces power consumption by a microprocessor with operand-value-based clock gating. A bit detect unit detects the condition of a pre-determined number of bits of an operand. If the pre-determined number of bits are not necessary for executing the operand, a condition detect signal is generated. Gating logic receives the condition detect signal and initiates a gated clock signal. Latching circuitry or pre-charge circuitry receives the gated clock signal and disables the pre-determined number of bits, preventing the execution of unnecessary bits by the microprocessor and reducing the power consumed during execution. Operation packing improves microprocessor performance by packing narrow-width operations for parallel execution by the microprocessor. A bit detect unit detects the condition of a pre-determined number of bits of an operand and initiates a condition detect signal. Issue logic detects common operations within execution instructions and receives the condition detect signal, initiating an operation packing signal when common operations are ready to issue and the operands involved contain a pre-determined number of bits unnecessary for execution. Multiplexers receive the operation packing signal and move data from the lowermost bits of the operands to the upper sub-words of the source operand bus, creating a parallel sub-word operation. After execution, multiplexers move data from upper sub-words of the result onto the lowermost bit boundaries of the individual result operands.
摘要翻译：电路通过具有基于操作数的时钟门控的微处理器降低功耗。位检测单元检测操作数的预定位数的条件。如果预定的比特数不是执行操作数所必需的，则产生条件检测信号。门控逻辑接收状态检测信号并启动门控时钟信号。锁存电路或预充电电路接收门控时钟信号并禁用预定数量的位，防止微处理器执行不必要的位，并减少执行期间消耗的功耗。操作包装通过打包由微处理器并行执行的窄宽度操作来提高微处理器性能。位检测单元检测操作数的预定位数的条件并启动条件检测信号。发行逻辑检测执行指令中的常见操作，并接收条件检测信号，当公共操作准备发布时启动操作打包信号，并且所涉及的操作数包含执行不必要的预定位数。多路复用器接收操作打包信号，并将数据从操作数的最低位移动到源操作数总线的上部子字，创建并行子字操作。在执行之后，多路复用器将数据从结果的高位子字移动到单个结果操作数的最低位边界。

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