会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 1. 发明申请
    • ENTERPRISE RESOURCE PLANNING (ERP) INTEGRATOR SYSTEM AND METHOD
    • 企业资源规划(ERP)集成系统与方法
    • US20120215687A1
    • 2012-08-23
    • US13032722
    • 2011-02-23
    • Manish JAIN
    • Manish JAIN
    • G06Q40/00
    • G06Q20/10
    • The methods and systems described herein attempt to resolve the deficiencies of the conventional systems by using pre-loaded templates and extracting comprehensively populated payment files in an industry standard format for processing. In one embodiment, a computer-implemented method for generating a payment file comprises receiving, by a computer, a request for a payment to a beneficiary; receiving, by a computer, a selection of the beneficiary for payment; receiving, by a computer, a request to pay the beneficiary using a template; retrieving, by a computer, the template from a database, wherein the template has a plurality of business rules for completing a plurality of data fields; extracting, by a computer, information from a database to complete the data fields of the template; and generating, by a computer, a payment file by completing the data fields of the template according to the plurality of business rules.
    • 本文描述的方法和系统尝试通过使用预加载的模板并且以行业标准格式提取全面填充的支付文件来解决常规系统的缺陷以进行处理。 在一个实施例中,用于生成支付文件的计算机实现的方法包括由计算机接收对受益人的付款请求; 由计算机接收受益人的选择付款; 通过计算机接收使用模板支付受益人的请求; 由计算机从数据库检索模板,其中模板具有用于完成多个数据字段的多个业务规则; 由计算机提取来自数据库的信息以完成模板的数据字段; 以及通过根据所述多个业务规则完成所述模板的数据字段,由计算机生成支付文件。
    • 3. 发明授权
    • Enhancing speed of simulation of an IC design while testing scan circuitry
    • 在测试扫描电路时提高IC设计仿真的速度
    • US07925940B2
    • 2011-04-12
    • US11873800
    • 2007-10-17
    • Yogesh PandeyVijay Anand SankarManish Jain
    • Yogesh PandeyVijay Anand SankarManish Jain
    • G01R31/28G06F17/50G06F9/45
    • G06F11/267G01R31/318591G06F11/261
    • A computer is programmed to prepare a computer program for simulating operation of an integrated circuit (IC) chip, in order to test scan circuitry therein. The computer is programmed to trace a path through combinational logic in a design of the IC chip, starting from an output port of a first scan cell and ending in an input port of a second scan cell. If the first and second scan cells receive a common scan enable signal, then the computer generates at least a portion of the computer program, i.e. software to perform simulation of propagating a signal through the path conditionally, for example when the common scan enable signal is inactive and alternatively to skip performing simulation when the common scan enable signal is active. The computer stores the portion of the computer program in memory, for use with other such portions of the computer program.
    • 计算机被编程为准备用于模拟集成电路(IC)芯片的操作的计算机程序,以便测试其中的扫描电路。 计算机被编程为通过IC芯片的设计中的组合逻辑来跟踪路径,从第一扫描单元的输出端口开始并且终止于第二扫描单元的输入端口。 如果第一和第二扫描单元接收到共同的扫描使能信号,则计算机生成计算机程序的至少一部分,即软件,以执行有条件地通过路径传播信号的模拟,例如当共用扫描使能信号为 当共用扫描使能信号有效时跳过执行仿真。 计算机将计算机程序的一部分存储在存储器中,以与计算机程序的其他这样的部分一起使用。
    • 5. 发明授权
    • System and method for enhancing the speed of dynamic timing simulation using delay assessment at compile time
    • 在编译时使用延迟评估来提高动态时序仿真的速度的系统和方法
    • US07047175B1
    • 2006-05-16
    • US10015180
    • 2001-11-16
    • Manish JainBadri P. Gopalan
    • Manish JainBadri P. Gopalan
    • G06F17/50
    • G06F17/5031
    • A method and system for reducing the time required for execution of the dynamic timing simulation for a logic simulator. For a logic circuit simulator having a compilation phase and a runtime phase, a delay assessment is performed during the compilation phase in order to identify storage elements that are exempt from possible timing violations at runtime. The runtime timing checks are removed from the exempt storage elements, thereby reducing the runtime calculation effort. Additionally, combinational portions of the circuit that drive the exempt storage elements are examined for element delays that can be effectively eliminated (e.g., zero delayed) from the runtime calculations, thereby providing a further reduction in the computational overhead via the use of cycle based simulation for these.
    • 一种用于减少执行逻辑模拟器的动态定时仿真所需的时间的方法和系统。 对于具有编译阶段和运行时阶段的逻辑电路模拟器,在编译阶段期间执行延迟评估,以便识别在运行时免除可能的定时违反的存储元件。 运行时定时检查从免除存储元件中移除,从而减少运行时计算工作。 此外,驱动免除存储元件的电路的组合部分被检查可以从运行时计算中有效地消除(例如,零延迟)的元件延迟,从而通过使用基于循环的仿真进一步减少计算开销 对于这些。
    • 9. 发明申请
    • SYSTEM AND METHOD FOR PROVIDING CUSTOMIZED APPLICATIONS ON DIFFERENT DEVICES
    • 用于在不同设备上提供定制应用的系统和方法
    • US20110153612A1
    • 2011-06-23
    • US12785541
    • 2010-05-24
    • Sanjoy PAULManish JAIN
    • Sanjoy PAULManish JAIN
    • G06F15/173G06F17/30
    • G06F16/9577
    • A method for providing a customized application on different requesting device types of a user is provided. The method enables, firstly, receiving requests made by the user using the different device types over multiple communication channels. Secondly, the method enables assigning a rank to the user based on requests received and one or more rules. Further the method enables determining personalization information based on the ranking. Finally, the method enables rendering a customized application on the different device types based on the personalization information and configuration information stored in a central data repository. The configuration information is related to the application and features thereof based on the user's subscription profile.
    • 提供了一种用于在用户的不同请求设备类型上提供定制应用的方法。 该方法首先通过多个通信信道接收用户使用不同设备类型的请求。 其次,该方法使得能够基于所接收的请求和一个或多个规则向用户分配等级。 此外,该方法能够基于排名来确定个性化信息。 最后,该方法使得能够基于存储在中央数据存储库中的个性化信息和配置信息,在不同的设备类型上呈现定制的应用。 配置信息基于用户的订阅简档与应用及其特征相关。