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1. 发明授权

US07446549B2 Semiconductor leakage current detector and leakage current measurement method, semiconductor leakage current detector with voltage trimming function and reference voltage trimming method, and semiconductor integrated circuit thereof 有权
标题翻译：半导体漏电流检测器和漏电流测量方法，具有调压功能和参考电压调整方法的半导体漏电检测器及其半导体集成电路
公开(公告)号：US07446549B2
公开(公告)日：2008-11-04
申请号：US11614127
申请日：2006-12-21
申请人： Yasuhiro Tomita , Manabu Komiya , Hitoshi Suwa , Toshiki Mori
发明人： Yasuhiro Tomita , Manabu Komiya , Hitoshi Suwa , Toshiki Mori
IPC分类号： G01R31/02 , G01R19/14 , G01R31/08 , H03K5/22 , G08B21/00
CPC分类号： G01R31/3008 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor leakage current detector of the present invention includes a first analog switch which causes a current to be measured to flow or to be cut off, a second analog switch which causes a reference current to flow or to be cut off, an integral capacitance element which is connected by the first analog switch and the second analog switch and is charged with the current to be measured or the reference current, a discharge unit which discharges the integral capacitor, and a comparison unit which compares the reference voltage with each of an integral voltage generated in the integral capacitor by a reference current after the discharge of the integral capacitor and an integral voltage generated in the integral capacitance element by the current to be measured after the discharge of the integral capacitor.
摘要翻译：本发明的半导体泄漏电流检测器包括使得测量电流流动或切断的第一模拟开关，引起参考电流流动或被切断的第二模拟开关，积分电容元件其通过第一模拟开关和第二模拟开关连接，并对被测量电流或参考电流进行充电;放电单元，其对积分电容器进行放电;以及比较单元，其将参考电压与积分电压在积分电容器放电之后，在积分电容器中产生的电压由积分电容器放电后的基准电流产生，积分电容元件中产生的积分电压由积分电容器放电后的待测电流产生。

2. 发明授权

US07313649B2 Flash memory and program verify method for flash memory 有权
标题翻译：闪存的闪存和程序验证方法
公开(公告)号：US07313649B2
公开(公告)日：2007-12-25
申请号：US11116440
申请日：2005-04-28
申请人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Allan Jacob , Avi Parvin , Noam Eshel
发明人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Allan Jacob , Avi Parvin , Noam Eshel
IPC分类号： G06F12/00
CPC分类号： G11C16/3454
摘要： In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuit 3 writes a fail value to a neighbor cell buffer 5 when all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer 5. The control circuit 3 verifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.
摘要翻译：在存储器单元共享位线的常规存储器阵列中，在程序验证过程中，单元电流流过相邻单元，因此，要被编程的存储器单元的阈值被错误地确定为较低。因此，在程序验证处理中，当从要被编程的存储单元的偏移量为n以下的所有相邻单元都处于被擦除状态时，控制电路3向相邻单元缓冲器5写入失败值，否则，将通过值写入邻居单元缓冲器5。控制电路3验证输入写入数据，并验证存储在相邻单元缓冲器中的数据。在后一验证过程中，使用高于常规验证电压的验证电压来补偿电池电流的泄漏。

3. 发明授权

US07035751B2 Nonvolatile memory microcomputer chip, and a method for testing the nonvolatile memory microcomputer chip 失效
标题翻译：非易失性存储器微计算机芯片，以及非易失性存储微计算机芯片的测试方法
公开(公告)号：US07035751B2
公开(公告)日：2006-04-25
申请号：US10694567
申请日：2003-10-28
申请人： Masatoshi Shinagawa , Akifumi Kawahara , Tetsuyuki Fukushima , Masakazu Kurata , Manabu Komiya
发明人： Masatoshi Shinagawa , Akifumi Kawahara , Tetsuyuki Fukushima , Masakazu Kurata , Manabu Komiya
IPC分类号： G06F19/00
CPC分类号： G11C29/1201 , G11C16/04 , G11C29/48 , G11C2029/0401 , G11C2029/2602
摘要： To provide a nonvolatile memory microcomputer with which a step of testing a microcomputer unit using a logic tester can be omitted, thereby reducing the testing cost. A memory tester supplies test data and expectation data to the nonvolatile memory microcomputer, and the nonvolatile memory microcomputer stores them in a nonvolatile memory. Subsequently, upon receiving an address signal, the nonvolatile memory outputs a test signal and an expectation signal based on test data and expectation data corresponding to the address signal. The test signal is supplied to a circuit block in the microcomputer unit, to drive the circuit block. The circuit block returns a test result signal, which is output to the memory tester together with the expectation signal. The memory tester compares the test result signal and the expectation signal, to judge whether the microcomputer unit operates correctly.
摘要翻译：为了提供一种非易失性存储微计算机，可以省略使用逻辑测试仪测试微型计算机单元的步骤，从而降低测试成本。存储器测试器将测试数据和期望数据提供给非易失性存储微计算机，并且非易失性存储器微计算机将它们存储在非易失性存储器中。随后，在接收到地址信号时，非易失性存储器基于与地址信号对应的测试数据和期望数据输出测试信号和期望信号。测试信号被提供给微计算机单元中的电路块，以驱动电路块。电路块返回测试结果信号，并将其与期望信号一起输出到存储器测试仪。存储器测试仪将测试结果信号和期望信号进行比较，以判断微机单元是否正常工作。

4. 发明申请

US20050237826A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050237826A1
公开(公告)日：2005-10-27
申请号：US11099605
申请日：2005-04-06
申请人： Hitoshi Suwa , Manabu Komiya , Yasuhiro Tomita
发明人： Hitoshi Suwa , Manabu Komiya , Yasuhiro Tomita
IPC分类号： G11C16/06 , G11C7/00 , G11C11/34 , G11C16/10
CPC分类号： G11C16/10
摘要： An n-bit status signal indicating an execution state of a write command is outputted from a status register. At the time of data writing, an output switching circuit outputs (n×m)-bit data in which a status signal pattern repeats m times. At the time of data reading, the output switching circuit outputs data stored in a memory cell array.
摘要翻译：从状态寄存器输出表示写命令执行状态的n位状态信号。在数据写入时，输出切换电路输出状态信号模式重复m次的（n×m）位数据。在数据读取时，输出切换电路输出存储在存储单元阵列中的数据。

5. 发明授权

US07310277B2 Non-volatile semiconductor storage device with specific command enable/disable control signal 有权
标题翻译：具有特定命令的非易失性半导体存储器件使能/禁止控制信号
公开(公告)号：US07310277B2
公开(公告)日：2007-12-18
申请号：US11113046
申请日：2005-04-25
申请人： Manabu Komiya , Yasuhiro Tomita , Hitoshi Suwa
发明人： Manabu Komiya , Yasuhiro Tomita , Hitoshi Suwa
IPC分类号： G11C7/00
CPC分类号： G11C16/22
摘要： The non-volatile semiconductor storage device 101 includes the specific command Enable/Disable signal lines 120 connected to the command decoder 108. The specific command Enable/Disable signals are externally inputted to the command decoder 108 through the signal lines 120. Thereby, when the device 101 is initialized, the command decoder 108 enables the specific command and the device 101 can shift to a mode corresponding to the specific command. On the other hand, the command decoder 108 can disable the specific command, for example, when a user uses the device 101, thereby preventing the specific command from being executed even when the specific command is erroneously issued.
摘要翻译：非易失性半导体存储装置101包括连接到命令解码器108的特定命令启用/禁止信号线120。特定命令使能/禁止信号通过信号线120被外部输入到命令解码器108。因此，当初始化设备101时，命令解码器108启用特定命令，并且设备101可以转换到与特定命令相对应的模式。另一方面，命令解码器108可以例如当用户使用设备101时禁止特定命令，从而即使在特定命令被错误地发出时也防止特定命令被执行。

6. 发明申请

US20050243616A1 Non-volatile semiconductor storage device 有权
标题翻译：非易失性半导体存储装置
公开(公告)号：US20050243616A1
公开(公告)日：2005-11-03
申请号：US11113046
申请日：2005-04-25
申请人： Manabu Komiya , Yasuhiro Tomita , Hitoshi Suwa
发明人： Manabu Komiya , Yasuhiro Tomita , Hitoshi Suwa
IPC分类号： G11C16/02 , G11C11/34 , G11C16/22
CPC分类号： G11C16/22
摘要： The non-volatile semiconductor storage device 101 includes the specific command Enable/Disable signal lines 120 connected to the command decoder 108. The specific command Enable/Disable signals are externally inputted to the command decoder 108 through the signal lines 120. Thereby, when the device 101 is initialized, the command decoder 108 enables the specific command and the device 101 can shift to a mode corresponding to the specific command. On the other hand, the command decoder 108 can disable the specific command, for example, when a user uses the device 101, thereby preventing the specific command from being executed even when the specific command is erroneously issued.
摘要翻译：非易失性半导体存储装置101包括连接到命令解码器108的特定命令启用/禁止信号线120。特定命令使能/禁止信号通过信号线120被外部输入到命令解码器108。因此，当初始化设备101时，命令解码器108启用特定命令，并且设备101可以转换到与特定命令相对应的模式。另一方面，命令解码器108可以例如当用户使用设备101时禁止特定命令，从而即使在特定命令被错误地发出时也防止特定命令被执行。

7. 发明申请

US20050286299A1 Flash memory and program verify method for flash memory 有权
标题翻译：闪存的闪存和程序验证方法
公开(公告)号：US20050286299A1
公开(公告)日：2005-12-29
申请号：US11116440
申请日：2005-04-28
申请人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Jacob , Avi Parvin , Noam Eshel
发明人： Yasuhiro Tomita , Hitoshi Suwa , Manabu Komiya , Tamas Toth , Jeffrey Jacob , Avi Parvin , Noam Eshel
IPC分类号： G11C11/34 , G11C16/34
CPC分类号： G11C16/3454
摘要： In conventional memory arrays in which a bit line is shared by memory cells, a cell current flows over into neighbor cell(s) in a program verify process, and therefore, the threshold of a memory cell to be programmed is erroneously determined to be lower. Therefore, in a program verify process, a control circuit 3 writes a fail value to a neighbor cell buffer 5 when all neighbor cell(s) having an offset of n or less from a memory cell to be programmed are in the erased state, and when otherwise, writes a pass value to the neighbor cell buffer 5. The control circuit 3 verifies input write data and also verifies data stored in the neighbor cell buffer(s). In the latter verify process, a verify voltage higher than an ordinary one is used to compensate for the leakage of cell current.
摘要翻译：在存储器单元共享位线的常规存储器阵列中，在程序验证过程中，单元电流流过相邻单元，因此，要被编程的存储器单元的阈值被错误地确定为较低。因此，在程序验证处理中，当从要被编程的存储单元的偏移量为n以下的所有相邻单元都处于被擦除状态时，控制电路3向相邻单元缓冲器5写入失败值，否则，将通过值写入邻居单元缓冲器5。控制电路3验证输入写入数据，并验证存储在相邻单元缓冲器中的数据。在后一验证过程中，使用高于常规验证电压的验证电压来补偿电池电流的泄漏。

8. 发明申请

US20070145981A1 SEMICONDUCTOR LEAKAGE CURRENT DETECTOR AND LEAKAGE CURRENT MEASUREMENT METHOD, SEMICONDUCTOR LEAKAGE CURRENT DETECTOR WITH VOLTAGE TRIMMING FUNCTION AND REFERENCE VOLTAGE TRIMMING METHOD, AND SEMICONDUCTOR INTERGRATED CIRCUIT THEREOF 有权
标题翻译：半导体漏电流检测器和泄漏电流测量方法，具有电压调制功能的半导体漏电流检测器和参考电压调制方法及其半导体集成电路
公开(公告)号：US20070145981A1
公开(公告)日：2007-06-28
申请号：US11614127
申请日：2006-12-21
申请人： Yasuhiro TOMITA , Manabu KOMIYA , Hitoshi SUWA , Toshiki MORI
发明人： Yasuhiro TOMITA , Manabu KOMIYA , Hitoshi SUWA , Toshiki MORI
IPC分类号： G01R31/14
CPC分类号： G01R31/3008 , G11C29/02 , G11C29/025 , G11C29/028 , G11C29/50 , G11C2029/1204 , G11C2029/5006
摘要： A semiconductor leakage current detector of the present invention includes a first analog switch which causes a current to be measured to flow or to be cut off, a second analog switch which causes a reference current to flow or to be cut off, an integral capacitance element which is connected by the first analog switch and the second analog switch and is charged with the current to be measured or the reference current, a discharge unit which discharges the integral capacitor, and a comparison unit which compares the reference voltage with each of an integral voltage generated in the integral capacitor by a reference current after the discharge of the integral capacitor and an integral voltage generated in the integral capacitance element by the current to be measured after the discharge of the integral capacitor
摘要翻译：本发明的半导体泄漏电流检测器包括使得测量电流流动或切断的第一模拟开关，引起参考电流流动或被切断的第二模拟开关，积分电容元件其通过第一模拟开关和第二模拟开关连接，并对被测量电流或参考电流进行充电;放电单元，其对积分电容器进行放电;以及比较单元，其将参考电压与积分电压积分电容器中产生的电压通过积分电容器放电后的基准电流产生，积分电容元件中产生的积分电压由积分电容器放电后的被测电流

9. 发明授权

US07110305B2 Nonvolatile semiconductor memory device for outputting a status signal having an output data width wider than an input data width 有权
标题翻译：非易失性半导体存储器件，用于输出具有比输入数据宽度宽的输出数据宽度的状态信号
公开(公告)号：US07110305B2
公开(公告)日：2006-09-19
申请号：US11099605
申请日：2005-04-06
申请人： Hitoshi Suwa , Manabu Komiya , Yasuhiro Tomita
发明人： Hitoshi Suwa , Manabu Komiya , Yasuhiro Tomita
IPC分类号： G11C7/10
CPC分类号： G11C16/10
摘要： An n-bit status signal indicating an execution state of a write command is outputted from a status register. At the time of data writing, an output switching circuit outputs (n×m)-bit data in which a status signal pattern repeats m times. At the time of data reading, the output switching circuit outputs data stored in a memory cell array.
摘要翻译：从状态寄存器输出表示写命令执行状态的n位状态信号。在数据写入时，输出切换电路输出状态信号模式重复m次的（n×m）位数据。在数据读取时，输出切换电路输出存储在存储单元阵列中的数据。

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