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1. 发明授权

US06303495B2 Method of forming thin copper film and semiconductor device with thin copper film 失效
标题翻译：铜薄膜形成方法及铜薄膜半导体器件
公开(公告)号：US06303495B2
公开(公告)日：2001-10-16
申请号：US09038117
申请日：1998-03-11
申请人： Takeshi Mori , Tetsuo Fukada , Makiko Hasegawa , Yoshihiko Toyoda
发明人： Takeshi Mori , Tetsuo Fukada , Makiko Hasegawa , Yoshihiko Toyoda
IPC分类号： H01L2144
CPC分类号： H01L21/76843 , C23C16/0272 , C23C16/18 , H01L21/32051 , H01L21/76858 , H01L21/76876
摘要： Copper material is exposed on the surface of a TiN film (an underlying film) formed in the main surface of a silicon substrate with a silicon oxide film interposed. Subsequently, a thin copper film is formed on TiN film. Thus, the thin copper film can be formed on the film including metal with high melting point or nitride thereof with high adhesion by means of CVD.
摘要翻译：在硅衬底的主表面上形成有氧化硅膜的TiN膜（底层膜）的表面上露出铜材料。随后，在TiN膜上形成薄的铜膜。因此，可以通过CVD在具有高熔点的金属或其氮化物的膜上形成具有高粘附性的薄膜。

2. 发明授权

US06184124B2 Method of making embedded wiring system 失效
标题翻译：嵌入式布线系统的制作方法
公开(公告)号：US06184124B2
公开(公告)日：2001-02-06
申请号：US09078510
申请日：1998-05-14
申请人： Makiko Hasegawa , Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada
发明人： Makiko Hasegawa , Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada
IPC分类号： H01L214763
CPC分类号： H01L21/76849 , H01L21/76844 , H01L21/76847 , H01L23/53233 , H01L23/53238 , H01L2924/0002 , H01L2924/00
摘要： A method of preparing a multilevel embedded wiring system for an IC comprising a first wiring formation step, a first connecting portion formation step, and a second wiring formation step, wherein the first wiring formation step comprises forming a first trench for a first embedded wiring in a first insulating layer disposed on a substrate and embedding in the first trench, in turn, a first conductive layer and a first conductive capping layer; the first connecting portion formation step comprises forming a second insulating layer on the first insulating layer and the first conductive capping layer, forming a via-hole in a part of the second insulating layer at the first conductive capping layer, and embedding a conductive connecting portion in the via-hole and connected to the first conductive layer; and the second formation step comprises forming a third insulating layer on the second insulating layer and the conductive connecting portion, forming a second trench for a second wiring in the third insulating layer at the conductive connecting portion, and embedding a second conductive layer in the second trench and connected to the conductive connecting portion.
摘要翻译：一种制备用于IC的多层嵌入式布线系统的方法，包括：第一布线形成步骤，第一连接部分形成步骤和第二布线形成步骤，其中所述第一布线形成步骤包括：形成用于第一嵌入布线的第一沟槽第一绝缘层，设置在基板上并嵌入第一沟槽中，依次具有第一导电层和第一导电覆盖层; 第一连接部分形成步骤包括在第一绝缘层和第一导电覆盖层上形成第二绝缘层，在第一导电覆盖层的第二绝缘层的一部分中形成通孔，并且将导电连接部分在所述通孔中并连接到所述第一导电层; 并且第二形成步骤包括在第二绝缘层和导电连接部分上形成第三绝缘层，在导电连接部分处在第三绝缘层中形成用于第二布线的第二沟槽，并在第二绝缘层中嵌入第二导电层沟槽并连接到导电连接部分。

3. 发明授权

US5793112A Multilevel embedded wiring system 失效
标题翻译：多层嵌入式布线系统
公开(公告)号：US5793112A
公开(公告)日：1998-08-11
申请号：US715446
申请日：1996-09-18
申请人： Makiko Hasegawa , Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada
发明人： Makiko Hasegawa , Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada
IPC分类号： H01L21/3205 , H01L23/52 , H01L23/532 , H01L23/538 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76849 , H01L21/76844 , H01L21/76847 , H01L23/53233 , H01L23/53238 , H01L2924/0002
摘要： The multilevel embedded wiring system for an IC has a capping layer on the conductive layer in channels or trenches in insulating layers. The capping layer prevents halation of light in a lithography process, resulting in a high precision structure. Even if Cu is used as the conductive material, the resulting wiring resistivity is still low and the diffusion and oxidation of Cu are prevented.
摘要翻译：用于IC的多电平嵌入式布线系统在绝缘层中的通道或沟槽中的导电层上具有覆盖层。封盖层防止光刻过程中的光晕，导致高精度结构。即使使用Cu作为导电材料，所得的布线电阻率仍然较低，并且防止了Cu的扩散和氧化。

4. 发明授权

US6107687A Semiconductor device having interconnection and adhesion layers 失效
标题翻译：具有互连和粘附层的半导体器件
公开(公告)号：US6107687A
公开(公告)日：2000-08-22
申请号：US39388
申请日：1998-03-16
申请人： Tetsuo Fukada , Takeshi Mori , Makiko Hasegawa , Yoshihiko Toyoda
发明人： Tetsuo Fukada , Takeshi Mori , Makiko Hasegawa , Yoshihiko Toyoda
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/52 , H01L23/532 , H01L23/48 , H01L29/40
CPC分类号： H01L21/76865 , H01L21/76849 , H01L21/76858 , H01L23/53238 , H01L2924/0002
摘要： A Cu interconnection layer is formed in a trench provided in an insulating layer with a base layer interposed therebetween, an adhesion layer is formed on the Cu interconnection layer and a cap layer is formed on the adhesion layer to restrict exfoliation of the cap layer formed on the Cu interconnection layer buried in the trench formed in the insulating layer.
摘要翻译：在设置在绝缘层中的沟槽中形成Cu互连层，其中介于基底层之间，在Cu互连层上形成粘合层，并且在粘合层上形成覆盖层，以限制形成在其上的覆盖层的剥离所述Cu互连层埋在形成在绝缘层中的沟槽中。

5. 发明授权

US5892286A Semiconductor device and manufacturing method thereof 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US5892286A
公开(公告)日：1999-04-06
申请号：US759999
申请日：1996-12-03
申请人： Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada , Makiko Hasegawa
发明人： Yoshihiko Toyoda , Takeshi Mori , Tetsuo Fukada , Makiko Hasegawa
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3205 , H01L21/768 , H01L23/528 , H01L23/532 , H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/53233 , H01L21/31116 , H01L21/76816 , H01L23/5283 , H01L23/53223 , H01L2924/0002
摘要： To form a plurality of patterned conductor leads in the same layer of an integrated circuit, an insulating film is etched to form a plurality of patterned grooves by plasma etching using an etching gas containing carbon and fluorine to which an additive gas containing carbon is added. The etching rate is substantially proportional to the groove width, so that the groove depth is substantially proportional to the groove width. Grooves are filled with a conductive material to form patterned conductor leads. Thus, an aspect ratio of the patterned conductor leads is kept in a certain range, resulting in an improvement in yield and reliability of the conductor leads. The conductor leads formed of material containing copper are coated with a diffusion preventive film.
摘要翻译：为了在集成电路的同一层中形成多个图案化的导体引线，通过使用含有碳和氟的蚀刻气体，通过等离子体蚀刻来蚀刻绝缘膜以形成多个图案化的凹槽，添加含有碳的添加气体。蚀刻速率基本上与凹槽宽度成比例，使得凹槽深度基本上与凹槽宽度成比例。沟槽填充有导电材料以形成图案化导体引线。因此，图案化的导体引线的纵横比保持在一定范围内，导致导体引线的产量和可靠性的提高。由含有铜的材料形成的导体引线涂覆有防扩散膜。

6. 发明授权

US6039808A CVD apparatus for Cu formation 失效
标题翻译： Cu形成用CVD装置
公开(公告)号：US6039808A
公开(公告)日：2000-03-21
申请号：US42693
申请日：1998-03-17
申请人： Yoshihiko Toyoda , Tetsuo Fukada , Takeshi Mori , Makiko Hasegawa
发明人： Yoshihiko Toyoda , Tetsuo Fukada , Takeshi Mori , Makiko Hasegawa
IPC分类号： C23C16/14 , C23C16/18 , C23C16/44 , H01L21/205 , H01L21/285 , C23C16/06
CPC分类号： C23C16/4404 , C23C16/18
摘要： In a CVD apparatus for Cu formation using as a raw material, a mixture of a solvent and a liquid raw material including Cu(HFA) and adducted molecules or a solid raw material including Cu(HFA) and adducted molecules, a fluorinated organic polymer contained, a fluorinated metal, an insulator or a Ti compound is provided on a surface of a member at a portion where the raw material exists.
摘要翻译：在作为原料的Cu形成用CVD装置中，溶剂和包含Cu（HFA）和加合分子的液体原料或包含Cu（HFA）和加成分子的固体原料的混合物含有含氟有机聚合物在原料存在的部分的表面上设置氟化金属，绝缘体或Ti化合物。

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