会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 3. 发明授权
    • Method and apparatus for manipulating an ATM cell
    • US07046673B2
    • 2006-05-16
    • US09916096
    • 2001-07-26
    • Mahesh N. GanmukhiBrian L. Jordan
    • Mahesh N. GanmukhiBrian L. Jordan
    • H04L12/56
    • H04L12/5601H04L49/107H04L49/108H04L49/3081H04L2012/5681H04Q11/0478
    • The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I≧1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O≧1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle. The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.
    • 4. 发明授权
    • Method and apparatus for switching, multicasting multiplexing and
demultiplexing an ATM cell
    • 用于切换,组播多路复用和解复用ATM信元的方法和装置
    • US5548588A
    • 1996-08-20
    • US381112
    • 1995-01-31
    • Mahesh N. GanmukhiBrian L. Jordan
    • Mahesh N. GanmukhiBrian L. Jordan
    • H04Q3/00H04L12/56H04Q11/04
    • H04L12/5601H04L49/108H04L49/203H04L49/3081H04Q11/0478H04L2012/5672
    • The present invention pertains to an apparatus for manipulating ATM cells. The apparatus comprises a memory array in which an entire ATM cell can be read or written in one read or write cycle. The apparatus is also comprised of a mechanism for reading or writing the entire ATM cell from or into the memory array. The present invention pertains to a method for switching an ATM cell. The method comprises the steps of receiving the ATM cell at a first input port of a switch from the ATM network. Then there can be the step of storing the ATM cell in one clock cycle in a memory array of the switch. Next there is the step of reading the ATM cell in the memory array in one clock cycle. Next there is the step of transferring the ATM cell from the memory array to a first output port of the switch. Next there is the step of transmitting the ATM cell from the first output port to the ATM network. The present invention pertains to a switch for an ATM cell. The switch comprises I input ports which receive ATM cells from an ATM network, where I.gtoreq.1 and is an integer. The switch is also comprised of a memory array connected to the I input ports for storing an ATM cell received by one of the I input ports in one clock cycle. The switch also comprises O output ports connected to the memory array, where O.gtoreq.1 and is an integer. One of the O output ports transmit an ATM cell which is received from the memory array to the ATM network. Additionally, the switch comprises a controller connected to the memory array, I input ports and O output ports for controlling the storage of an ATM cell from one of the input ports into the memory array in one clock cycle. The switch can be used for normal switching operation, multicasting, demultiplexing or multiplexing.
    • 本发明涉及一种用于操纵ATM信元的装置。 该装置包括存储器阵列,其中可以在一个读或写周期中读取或写入整个ATM信元。 该装置还包括用于从存储器阵列读取或写入整个ATM信元的机构。 本发明涉及一种用于切换ATM信元的方法。 该方法包括以下步骤:在ATM网络的交换机的第一输入端口处接收ATM信元。 然后,可以在交换机的存储器阵列中的一个时钟周期中存储ATM信元的步骤。 接下来是在一个时钟周期内读取存储器阵列中的ATM单元的步骤。 接下来,存在将ATM信元从存储器阵列传送到交换机的第一输出端口的步骤。 接下来,将ATM信元从第一输出端口发送到ATM网络的步骤。 本发明涉及ATM信元的交换机。 该交换机包括从ATM网络接收ATM信元的I个输入端口,其中I> / = 1并且是整数。 开关还包括连接到I输入端口的存储器阵列,用于存储在一个时钟周期中由I个输入端口之一接收的ATM信元。 交换机还包括连接到存储器阵列的O输出端口,其中O> / = 1并且是整数。 O输出端口中的一个发送从存储器阵列接收到ATM网络的ATM信元。 此外,开关包括连接到存储器阵列的控制器,I输入端口和O输出端口,用于在一个时钟周期内控制ATM信元从一个输入端口存储到存储器阵列中。 该交换机可用于正常的切换操作,组播,解复用或多路复用。
    • 5. 发明授权
    • Parallel computer system
    • 并行计算机系统
    • US5333268A
    • 1994-07-26
    • US946242
    • 1992-09-16
    • David C. DouglasMahesh N. GanmukhiJeffrey V. HillW. Daniel HillisBradley C. KuszmaulCharles E. LeisersonDavid S. WellsMonica C. WongShaw-Wen YangRobert C. Zak
    • David C. DouglasMahesh N. GanmukhiJeffrey V. HillW. Daniel HillisBradley C. KuszmaulCharles E. LeisersonDavid S. WellsMonica C. WongShaw-Wen YangRobert C. Zak
    • G06F15/16G06F11/00G06F11/08G06F11/22G06F15/173G06F15/80
    • G06F15/17381G06F11/08G06F11/22G06F11/324G06F15/17343H04L45/48H04L49/35H04L49/555G06F2201/88
    • A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.
    • 数字计算机包括多个处理元件,命令处理器,诊断处理器和通信网络。 处理元件各自执行与命令相关的数据处理和数据通信操作。 处理元件还响应诊断操作请求执行诊断操作,并响应于此提供诊断结果。 命令处理器为处理元件生成命令,并且还响应诊断操作请求执行诊断操作并响应于此提供诊断结果。 诊断处理器产生诊断请求。 通信网络包括三个元件,包括数据路由器,控制网络和诊断网络。 数据路由器连接到处理元件,以便在数据通信操作期间便于它们之间的数据传输。 控制网络连接到处理元件和命令处理器,用于将命令从命令处理器传送到处理元件。 连接到处理元件的诊断网络,命令处理器和诊断处理器,用于将诊断请求从诊断处理器传送到处理元件和命令处理器,并将诊断结果从处理元件和命令处理器传送到诊断处理器。
    • 10. 发明授权
    • Method and apparatus for performing cut-through virtual circuit merging
    • 执行切换虚拟电路合并的方法和装置
    • US06233243B1
    • 2001-05-15
    • US08976759
    • 1997-11-24
    • Mahesh N. GanmukhiPrasasth R. Palnati
    • Mahesh N. GanmukhiPrasasth R. Palnati
    • H04L1254
    • H04L45/40H04L43/0811H04L45/06H04L45/28
    • A method and apparatus for performing virtual connection merging in an output port of a network switch are disclosed. In the event no completely assembled packets have been received and scheduled for transmission, a partially received packet is selected for cut-through transmission prior to receipt of all cells comprising the packet. Transmission of the selected packet is initiated and a timer is started. If the timer expires prior to the receipt of an end of packet indication for the packet for which transmission has commenced, and end of packet signal is generated and transmitted and the transmission of additional cells for the cut-through packet is aborted. In this manner, delays associated with packet reassembly may be avoided and buffer sizes of reassembly buffers may be reduced.
    • 公开了一种用于在网络交换机的输出端口中执行虚拟连接合并的方法和装置。 在没有完全组装的分组已经被接收并被调度用于传输的情况下,在接收到包括分组的所有小区之前,选择部分接收的分组用于直通传输。 启动所选分组的传输并启动定时器。 如果定时器在接收到已经开始发送的分组的分组指示的结束之前到期,并且分组信号的结束被生成和发送,并且中断分组的附加小区的传输被中止。 以这种方式,可以避免与分组重组相关联的延迟,并且可以减少重组缓冲器的缓冲器大小。