专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明申请

WO2010078187A3 STATE HISTORY STORAGE FOR SYNCHRONIZING REDUNDANT PROCESSORS 审中-公开
公开(公告)号：WO2010078187A3
公开(公告)日：2010-07-08
申请号：PCT/US2009/069384
申请日：2009-12-23
申请人： INTEL CORPORATION , MUKHERJEE, Shubhendu S. , BISWAS, Arijit , RAASSCH, Steven , RACUNAS, Paul
发明人： MUKHERJEE, Shubhendu S. , BISWAS, Arijit , RAASSCH, Steven , RACUNAS, Paul
IPC分类号： G06F15/163 , G06F9/06 , G06F9/46 , G06F3/06
摘要： Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.

2. 发明申请

WO2005088458A2 A METHOD AND SYSTEM FOR COALESCING COHERENCE MESSAGES 审中-公开
标题翻译：一种用于混合相关信息的方法和系统
公开(公告)号：WO2005088458A2
公开(公告)日：2005-09-22
申请号：PCT/US2005007087
申请日：2005-03-04
申请人： INTEL CORP , MUKHERJEE SHUBHENDU
发明人： MUKHERJEE SHUBHENDU
IPC分类号： G06F12/08
CPC分类号： G06F12/0813 , G06F12/0828 , G06F12/0859
摘要： The ability to combine a plurality of remote read miss requests and/or a plurality of exclusive access requests into a single network packet for efficiently utilizing network bandwidth. This combination exists for a plurality of processors in a network configuration. In contrast, other solutions have inefficiently utilized network bandwidth by individually transmitting a plurality of remote read miss requests and/or a plurality of exclusive access requests via a plurality of network packets.
摘要翻译：将多个远程读取未命中请求和/或多个独占访问请求组合成单个网络分组以有效利用网络带宽的能力。这种组合存在于网络配置中的多个处理器。相反，其他解决方案通过经由多个网络分组单独发送多个远程读取未命中请求和/或多个独占访问请求而无效地利用网络带宽。

3. 发明申请

WO2010078187A2 STATE HISTORY STORAGE FOR SYNCHRONIZING REDUNDANT PROCESSORS 审中-公开
标题翻译：用于同步冗余处理器的状态存储
公开(公告)号：WO2010078187A2
公开(公告)日：2010-07-08
申请号：PCT/US2009069384
申请日：2009-12-23
申请人： INTEL CORP , MUKHERJEE SHUBHENDU S , BISWAS ARIJIT , RAASSCH STEVEN , RACUNAS PAUL
发明人： MUKHERJEE SHUBHENDU S , BISWAS ARIJIT , RAASSCH STEVEN , RACUNAS PAUL
IPC分类号： G06F15/163 , G06F3/06 , G06F9/06 , G06F9/46
CPC分类号： G06F15/16 , G06F11/1407 , G06F11/1641 , G06F11/1658 , G06F11/1683 , G06F11/1691
摘要： Embodiments of an invention for synchronizing redundant processors using state history are disclosed. In one embodiment, an apparatus includes two processors, state storage for each processor, and control logic. Each processor is to execute the same instructions. The state storage is to store compressed processor state information for each instruction executed by the processors. The control logic is to synchronize the two processors based on entries from the state storage.
摘要翻译：公开了使用状态历史来同步冗余处理器的发明的实施例。在一个实施例中，装置包括两个处理器，每个处理器的状态存储器和控制逻辑。每个处理器都要执行相同的指令。状态存储器是存储由处理器执行的每个指令的压缩处理器状态信息。控制逻辑是基于来自状态存储器的条目来同步两个处理器。

4. 发明申请

WO2006135937A2 SELECTIVE ACTIVATION OF ERROR MITIGATION BASED ON BIT LEVEL ERROR COUNT 审中-公开
标题翻译：基于位电平错误计数的错误缓解的选择性激活
公开(公告)号：WO2006135937A2
公开(公告)日：2006-12-21
申请号：PCT/US2006/023634
申请日：2006-06-13
申请人： INTEL CORPORATION , BISWAS, Arijit , RAASSCH, Steven , MUKHERJEE, Shubhendu
发明人： BISWAS, Arijit , RAASSCH, Steven , MUKHERJEE, Shubhendu
IPC分类号： G06F11/10
CPC分类号： G06F11/1637 , G06F11/076 , G06F11/1008 , G06F11/1076
摘要： Embodiments of apparatuses and methods for selective activation of error mitigation based on bit level error counts are disclosed. In one embodiment, an apparatus includes a plurality of state elements, an error counter, and activation logic. The error counter is to count the number of bit level errors in the state elements. The activation logic is to increase error mitigation if the number of bit level errors exceeds a threshold value.
摘要翻译：公开了基于比特级错误计数的用于选择性地激活误差减轻的装置和方法的实施例。在一个实施例中，装置包括多个状态元件，错误计数器和激活逻辑。错误计数器是对状态元素中的位级别错误的数量进行计数。如果比特级错误的数量超过阈值，则激活逻辑是增加错误缓解。

5. 发明申请

WO2006012284A2 AN APPARATUS AND METHOD FOR PACKET COALESCING WITHIN INTERCONNECTION NETWORK ROUTERS 审中-公开
标题翻译：在互连网络路由器中分组分组的装置和方法
公开(公告)号：WO2006012284A2
公开(公告)日：2006-02-02
申请号：PCT/US2005/022446
申请日：2005-06-24
申请人： INTEL CORPORATION , MUKHERJEE, Shubhendu, S.
发明人： MUKHERJEE, Shubhendu, S.
IPC分类号： G06F12/08
CPC分类号： G06F15/17375
摘要： A method and apparatus for packet coalescing within interconnection network routers. In one embodiment, the method includes the scan of at least one input buffer to identify at least two network packets that include coherence protocol messages and are directed to the same destination, but from different sources. In one embodiment, coherence protocol messages within the network packets are combined into a coalesced network packet. Once combined, the coalesced network packet is transmitted to the same or matching destination. In one embodiment, combining multiple network packets (each containing a single logical coherence message) into a larger, coalesced network packet amortizes the fixed overhead of sending a network packet including a single coherence message, as compared to the larger, coalesced network packet, to improve bandwidth usage. Other embodiments are described and claimed.
摘要翻译：用于互连网络路由器内的分组聚合的方法和装置。在一个实施例中，该方法包括扫描至少一个输入缓冲器以识别包括相干协议消息并且被引导到相同目的地但是来自不同来源的至少两个网络分组。在一个实施例中，网络分组内的相干协议消息被组合成合并的网络分组。一旦组合，合并的网络分组被发送到相同或匹配的目的地。在一个实施例中，将多个网络分组（每个包含单个逻辑相干消息）组合到更大的合并网络分组中，将与包括较大的合并网络分组相比的包括单个相干消息的网络分组的固定开销分摊到提高带宽使用率。描述和要求保护其他实施例。

6. 发明申请

WO2005121971A1 A MECHANISM TO INVALIDATE DATA TRANSLATION BUFFER ENTRIES IN A MULTIPROCESSOR SYSTEM 审中-公开
标题翻译：在多处理器系统中隐藏数据翻译缓冲区输入的机制
公开(公告)号：WO2005121971A1
公开(公告)日：2005-12-22
申请号：PCT/US2005/016557
申请日：2005-05-13
申请人： INTEL CORPORATION , MUKHERJEE, Shubhendu
发明人： MUKHERJEE, Shubhendu
IPC分类号： G06F12/10
CPC分类号： G06F12/1027 , G06F12/1072
摘要： According to one embodiment a computer system is disclosed. The computer system includes a first central processing unit (CPU) having a translation buffer (TB) to store virtual to physical address translations, and a snoop filter coupled to the first CPU to mirror the operation of the first TB and implemented to search for entries upon receiving an invalidation request from a second CPU.
摘要翻译：根据一个实施例，公开了一种计算机系统。计算机系统包括具有用于存储虚拟到物理地址转换的转换缓冲器（TB）的第一中央处理单元（CPU），以及耦合到第一CPU的窥探过滤器，以反映第一TB的操作并被实现为搜索条目在从第二CPU接收到无效请求时。

7. 发明申请

WO2009131924A2 DETECTING ARCHITECTURAL VULNERABILITY OF PROCESSOR RESOURCES 审中-公开
标题翻译：检测处理器资源的架构脆弱性
公开(公告)号：WO2009131924A2
公开(公告)日：2009-10-29
申请号：PCT/US2009/041074
申请日：2009-04-20
申请人： INTEL CORPORATION , BISWAS, Arijit , SOUNDARARAJAN, Niranjan , MUKHERJEE, Shubhendu
发明人： BISWAS, Arijit , SOUNDARARAJAN, Niranjan , MUKHERJEE, Shubhendu
IPC分类号： G06F17/00 , G06F9/00 , G06F11/00 , G06F13/00
CPC分类号： G06F11/3466 , G06F11/3409 , G06F2201/88 , Y02D10/34
摘要： In one embodiment, a quantum detector is provided to detect a vulnerability measure for a processor based on a processor metrics each associated with operation of a processor structure during a quantum, along with a controller to control an error mitigation unit based on the vulnerability measure. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，提供量子检测器，用于基于与量化期间的处理器结构的操作相关联的处理器度量，以及基于所述漏洞测量来控制误差减轻单元的控制器来检测处理器的脆弱性度量。描述和要求保护其他实施例。

8. 发明申请

WO2006039595A3 EXECUTING CHECKER INSTRUCTIONS IN REDUNDANT MULTITHREADING ENVIRONMENTS 审中-公开
标题翻译：执行检查员在冗余多元环境中的指示
公开(公告)号：WO2006039595A3
公开(公告)日：2006-06-29
申请号：PCT/US2005035375
申请日：2005-09-29
申请人： INTEL CORP , MUKHERJEE SHUBHENDU , EMER JOEL , REINHARDT STEVEN , WEAVER CHRISTOPHER
发明人： MUKHERJEE SHUBHENDU , EMER JOEL , REINHARDT STEVEN , WEAVER CHRISTOPHER
IPC分类号： G06F11/00 , G06F11/16
CPC分类号： G06F11/1494 , G06F11/1695
摘要： A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.
摘要翻译：描述用于冗余多线程环境中的检查指令的方法和装置。在一个实施例中，当RMT需要时，处理器可以在前导线程和后退线程中发出校验指令。检查器指令可以独立地沿着每个线程的各个管道下行，直到它到达每个管道末端的缓冲区。然后，在提交检查指令之前，检验员指令寻找其对应方，并对指令进行比较。如果检查器指令匹配，则检查器指令提交并退出，否则声明错误。

9. 发明申请

WO2005066780A3 MANAGING EXTERNAL MEMORY UPDATES FOR FAULT DETECTION IN REDUNDANT MULTITHREADING SYSTEMS USING SPECULATIVE MEMORY SUPPORT 审中-公开
标题翻译：使用分析性内存支持管理冗余多用户系统故障检测的外部存储器更新
公开(公告)号：WO2005066780A3
公开(公告)日：2006-05-04
申请号：PCT/US2004043649
申请日：2004-12-22
申请人： INTEL CORP , REINHARDT STEVEN K , MUKHERJEE SHUBHENDU , EMER JOEL S , WEAVER CHRISTOPHER T
发明人： REINHARDT STEVEN K , MUKHERJEE SHUBHENDU , EMER JOEL S , WEAVER CHRISTOPHER T
IPC分类号： G06F9/38 , G06F9/46 , G11C29/00 , G06F11/14
CPC分类号： G06F9/3851 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F11/1494 , G06F11/1497
摘要： A multithreaded architecture is disclosed for managing external memory updates for fault detection in redundant multithreading systems using speculative memory support. In particular, a method provides input replication of load values on a SRT processor by using speculative memory support to isolate redundant threads form external updates. This method thus avoids the need for dedicated structures to provide input replication.
摘要翻译：公开了一种多线程体系结构，用于管理使用推测性内存支持的冗余多线程系统中的故障检测的外部存储器更新。特别地，一种方法通过使用推测性内存支持将冗余线程从外部更新隔离，从而提供SRT处理器上负载值的输入复制。因此，该方法避免了专用结构提供输入复制的需要。

10. 发明申请

WO2006007147A1 METHOD AND APPARATUS FOR REDUCING FALSE ERROR DETECTION IN A MICROPROCESSOR 审中-公开
标题翻译：减少微处理器误差检测的方法和装置
公开(公告)号：WO2006007147A1
公开(公告)日：2006-01-19
申请号：PCT/US2005/017772
申请日：2005-05-20
申请人： INTEL CORPORATION , MUKHERJEE, Shubhendu , EMER, Joel , REINHARDT, Steven , WEAVER, Christopher , SMITH, Michael
发明人： MUKHERJEE, Shubhendu , EMER, Joel , REINHARDT, Steven , WEAVER, Christopher , SMITH, Michael
IPC分类号： G06F9/38
CPC分类号： G06F9/3865 , G06F11/10
摘要： A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.
摘要翻译：减少微处理器中的错误检测的技术。通过指令流程路径，通过指令传播pi位。当检测到奇偶校验错误时，设置pi位，而不是提高机器检查异常。到达提交点后，处理器可以确定指令是否在错误的路径上。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式