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1. 发明专利

JP2008059597A Parallel electronic design automation: shared simultaneous editing 审中-公开
标题翻译：并行电子设计自动化：共享同步编辑
公开(公告)号：JP2008059597A
公开(公告)日：2008-03-13
申请号：JP2007247641
申请日：2007-09-25
申请人： Mentor Graphics Corp , メンター・グラフィクス・コーポレーション
发明人： PFEIL CHARLES , SMITH EDWIN FRANKLIN , PETUNIN VLADIMIR , POTTS HENRY , NATARAJAN VENKAT
IPC分类号： G06F17/50 , G06F17/30 , H05K3/00
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/74
摘要： PROBLEM TO BE SOLVED: To enable users to work simultaneously in the shared area of PCB (Printed Circuit Board) design while attaining integrity of PCB design.
SOLUTION: A method for simultaneously allowing a plurality of users connected with a plurality of clients 202, 204, 206, to make editing requests for simultaneously editing in the shared area of main design contents, includes displaying the main design contents and enabling the first user to edit in the shared area on design, and enabling the second user to simultaneously edit in the shared area on design while maintaining integrity on design.
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：使用户能够在PCB设计的完整性的同时，在PCB（印刷电路板）设计的共享区域同时工作。解决方案：一种用于同时允许与多个客户端202,204,206连接的多个用户进行主设计内容的共享区域中的同时编辑的编辑请求的方法，包括显示主设计内容并使能第一个用户在设计中的共享区域中进行编辑，并使第二个用户能够在设计时在共享区域中同时进行编辑，同时保持设计的完整性。版权所有（C）2008，JPO＆INPIT

2. 发明专利

JP2006178498A Method and device for determining phase shifts and trim mask for integrated circuit 有权
标题翻译：用于确定集成电路的相位移动和TRIM MASK的方法和装置
公开(公告)号：JP2006178498A
公开(公告)日：2006-07-06
申请号：JP2006071816
申请日：2006-03-15
申请人： Mentor Graphics Corp , メンター・グラフィクス・コーポレーション
发明人： COBB NICOLAS BAILEY , SAKAJIRI KYOHEI
IPC分类号： G03F1/00 , G03F1/26 , G03F7/20 , H01L21/027
CPC分类号： G03F1/26 , G03F1/70 , G03F7/2026
摘要： PROBLEM TO BE SOLVED: To provide a method and a device for optimizing a deep sub-micron layout of an integrated circuit. SOLUTION: Components of an integrated circuit (IC) design (gates, for example) can be identified and manufactured using a phase shifting process to improve circuit density and/or performance as compared to a circuit manufactured without using phase shifting processes. In one embodiment, a first mask (a phase shift mask, for example) is generated that includes the component to be manufactured using the phase shifting process. A second mask (a trim mask, for example) is also generated to further process the structure created using the first mask. Both masks are defined based on a region (a diffusion region, for example) in a different layer of the integrated circuit layout than the structure (the gate, for example) being created with the phase shifting process. COPYRIGHT: (C)2006,JPO&NCIPI
摘要翻译：要解决的问题：提供一种用于优化集成电路的深亚微米布局的方法和装置。解决方案：与不使用相移过程制造的电路相比，可以使用相移过程来识别和制造集成电路（IC）设计（例如门）的组件，以提高电路密度和/或性能。在一个实施例中，生成包括使用相移处理来制造的部件的第一掩模（例如，相移掩模）。还生成第二个掩码（例如修剪蒙版），以进一步处理使用第一个掩码创建的结构。两个掩模基于集成电路布局的不同层中的区域（例如，扩散区域）来定义，该区域（例如，扩散区域）比通过相移处理创建的结构（例如栅极）定义。版权所有（C）2006，JPO＆NCIPI

3. 发明专利

JP2005051751A Regional time multiplexed emulation system 有权
标题翻译：区域时间多重仿真系统
公开(公告)号：JP2005051751A
公开(公告)日：2005-02-24
申请号：JP2004185152
申请日：2004-06-23
申请人： Mentor Graphics Corp , メンター・グラフィクス・コーポレーション
发明人： REBLEWSKI FREDERIC , LEPAPE OLIVIER , BARBIER JEAN
IPC分类号： G06F11/22 , G06F17/50 , H01L21/82 , H03K19/173
CPC分类号： G06F17/5027
摘要： PROBLEM TO BE SOLVED: To provide a regional time multiplexed emulation system. SOLUTION: The regional time multiplexed emulation system includes an emulator for emulating a circuit design. The emulator includes a plurality of reconfigurable logic circuit with buffered I/O pins and reconfigurable logic elements. The reconfigurable logic circuit is reconfigurable to emulate the circuit design using at least one user clock to clock the logic elements and at least one signal routing clock to time multiplex the routing of emulation signals between the reconfigurable logic circuits and to be independent of the user clock. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：提供区域时间复用仿真系统。
解决方案：区域时间复用仿真系统包括用于仿真电路设计的仿真器。仿真器包括具有缓冲I / O引脚和可重配置逻辑元件的多个可重构逻辑电路。可重配置逻辑电路是可重新配置的，以使用至少一个用户时钟来模拟电路设计来对逻辑元件和至少一个信号路由时钟进行时钟复用以在可重构逻辑电路之间复用仿真信号的路由，并且独立于用户时钟。版权所有（C）2005，JPO＆NCIPI

4. 发明专利

JP2004303234A Hierarchical evaluation of cell 审中-公开
公开(公告)号：JP2004303234A
公开(公告)日：2004-10-28
申请号：JP2004079512
申请日：2004-03-19
申请人： Mentor Graphics Corp , メンター・グラフィクス・コーポレーション
发明人： KRESH KOBI , BROOKS PHILIP A
IPC分类号： G06F17/50 , G01N20060101 , G06F9/45 , H01L21/82
CPC分类号： G06F17/5045 , G06F17/5068
摘要： PROBLEM TO BE SOLVED: To provide a method for evaluating cells in a hierarchical data structure.
SOLUTION: This cell hierarchical evaluation is provided with a method for deciding the hierarchical effects of cells in a data structure, and the hierarchical effectiveness indicates how effective the use of cells will be in executing a task by using the data structure. This cell hierarchy evaluation is also provided with a method for deciding the hierarchical effectiveness of all the cells in the data structure in order to decide which cell should be used for executing the task with the data structure.
COPYRIGHT: (C)2005,JPO&NCIPI

5. 发明专利

JP2011151423A Light source optimization for image fidelity and throughput 有权
标题翻译：光源优化用于图像的清晰度和穿透性
公开(公告)号：JP2011151423A
公开(公告)日：2011-08-04
申请号：JP2011103314
申请日：2011-05-02
申请人： Mentor Graphics Corp , メンター・グラフィクス・コーポレーション
发明人： GRANIK YURI
IPC分类号： H01L21/027 , G03F7/20 , G03H1/08
CPC分类号： G03F7/70491 , G03F7/70108 , G03F7/70441 , G03F7/705
摘要： PROBLEM TO BE SOLVED: To provide optimization of a light source suitable for image fidelity and throughput.
SOLUTION: This method is used for optimizing a light source to generate a desired feature pattern on a wafer by photolithography processing. The method includes steps of: receiving at least a part of a layout database to select the desired feature pattern to be generated on a wafer; associating a plurality of pixel densities in the light source and contribution of pixels of the light source to one point on the wafer with the desired feature pattern by using a mathematical relationship; and determining the pixel density of the light source by using the mathematical relationship so that an error between a feature pattern generated on the wafer and the desired feature pattern is minimized at simultaneous irradiation of the pixels at a predetermined pixel density.
COPYRIGHT: (C)2011,JPO&INPIT
摘要翻译：要解决的问题：提供适合于图像保真度和吞吐量的光源的优化。解决方案：该方法用于优化光源以通过光刻处理在晶片上产生期望的特征图案。该方法包括以下步骤：接收布局数据库的至少一部分以选择要在晶片上生成的期望特征图案; 通过使用数学关系将光源中的多个像素密度和光源的像素对晶片上的一个点的贡献与期望的特征图案相关联; 以及通过使用数学关系确定光源的像素密度，使得在以预定像素密度同时照射像素时，在晶片上产生的特征图案与期望特征图案之间的误差最小化。版权所有（C）2011，JPO＆INPIT

6. 发明专利

JP2010123146A Parallel electronic design automation: distributed simultaneous editing 有权
标题翻译：并行电子设计自动化：分布式同时编辑
公开(公告)号：JP2010123146A
公开(公告)日：2010-06-03
申请号：JP2010051188
申请日：2010-03-08
申请人： Mentor Graphics Corp , メンター・グラフィクス・コーポレーション
发明人： PFEIL CHARLES , SMITH EDWIN FRANKLIN
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/74
摘要： PROBLEM TO BE SOLVED: To provide a mechanism for giving a user a shared environment relative to parallel printed circuit board (PCB) design. SOLUTION: A method and apparatus are described for allowing multiple users to simultaneously edit a design while being able to view edits to the entire design (1404). A design (such as for a printed circuit board) having a plurality of exclusive areas is displayed to a plurality of users (1402). A first user checks out a corresponding section of the design, and edits the design (1406). A second user checks out a corresponding section of the design, and edits the design simultaneously with the first user editing the design (1406). COPYRIGHT: (C)2010,JPO&INPIT
摘要翻译：要解决的问题：提供一种用于给用户相对于并行印刷电路板（PCB）设计的共享环境的机制。描述了一种方法和装置，用于允许多个用户同时编辑设计，同时能够查看对整个设计的编辑（1404）。向多个用户（1402）显示具有多个专属区域的设计（例如，用于印刷电路板）。第一个用户检查设计的相应部分，并编辑设计（1406）。第二个用户检查设计的相应部分，并与第一个用户编辑设计同时编辑设计（1406）。版权所有（C）2010，JPO＆INPIT

7. 发明专利

JP2008186489A Parallel electronic design automation: distributed simultaneous editing 审中-公开
标题翻译：并行电子设计自动化：分布式同时编辑
公开(公告)号：JP2008186489A
公开(公告)日：2008-08-14
申请号：JP2008121618
申请日：2008-05-07
申请人： Mentor Graphics Corp , メンター・グラフィクス・コーポレーション
发明人： PFEIL CHARLES , SMITH EDWIN FRANKLIN
IPC分类号： G06F17/50
CPC分类号： G06F17/50 , G06F17/5068 , G06F2217/74
摘要： PROBLEM TO BE SOLVED: To provide a mechanism for giving users a shared environment for parallel printed circuit board (PCB) design.
SOLUTION: A method and apparatus are described for allowing multiple users to simultaneously edit a design while being able to view edits to the entire design (1404). A design (such as for printed circuit board) having a plurality of exclusive areas is displayed to a plurality of users (1402). A first user checks out a corresponding section of the design, and edits the design (1406), a second user checks out a corresponding section of the design, and edits the design simultaneously with the first user editing the design (1406).
COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：为用户提供平行印刷电路板（PCB）设计的共享环境的机制。描述了一种方法和装置，用于允许多个用户同时编辑设计，同时能够查看对整个设计的编辑（1404）。具有多个专属区域的设计（例如印刷电路板）被显示给多个用户（1402）。第一用户检查设计的相应部分，并且编辑设计（1406），第二用户检出设计的相应部分，并且与第一用户编辑设计同时编辑设计（1406）。版权所有（C）2008，JPO＆INPIT

8. 发明专利

JP2007280383A Distribution of parallel operations 审中-公开
标题翻译：并行运行的分配
公开(公告)号：JP2007280383A
公开(公告)日：2007-10-25
申请号：JP2007086909
申请日：2007-03-29
申请人： Mentor Graphics Corp , メンターグラフィックスコーポレイション
发明人： GRODD LAURENCE , TODD ROBERT A , TOMBLIN JIMMY J
IPC分类号： G06F9/48
CPC分类号： G06F9/5066
摘要： PROBLEM TO BE SOLVED: To suitably provide techniques to more efficiently distribute process data for software application among a plurality of computers. SOLUTION: Parallel operation sets for use by the software application are identified, each parallel operation set is then provided to a master computing thread for processing, together with its associated process data. Each master computing thread then provide its operation set to one or more slave computers based upon parallelism in the process data associated with its operation set. In this manner, the execution of operations by the software application is widely distributed among multiple networked computers based upon parallelism in both the process data used by the software and the operations executed by the software application. COPYRIGHT: (C)2008,JPO&INPIT
摘要翻译：要解决的问题：适当地提供技术以在多个计算机之间更有效地分发用于软件应用的过程数据。解决方案：识别软件应用程序使用的并行操作集合，然后将每个并行操作集合及其关联的进程数据提供给主计算线程进行处理。然后，每个主计算线程基于与其操作集相关联的过程数据中的并行性将其操作集提供给一个或多个从属计算机。以这种方式，软件应用的操作的执行基于软件使用的过程数据和由软件应用执行的操作的并行性被广泛分布在多个联网计算机之间。版权所有（C）2008，JPO＆INPIT

9. 发明专利

JP2007279759A Convergence technique for model-based optical proximity correction 审中-公开
标题翻译：基于模型的光学近似校正的综合技术
公开(公告)号：JP2007279759A
公开(公告)日：2007-10-25
申请号：JP2007148490
申请日：2007-06-04
申请人： Mentor Graphics Corp , メンター・グラフィクス・コーポレーション
发明人： COBB NICOLAS BAILEY , SAHOURIA EMILE
IPC分类号： G03F1/00 , G03F1/36 , G06F17/50 , H01L21/027
CPC分类号： G03F1/36 , G03F1/70 , G06F17/5081
摘要： PROBLEM TO BE SOLVED: To provide an optical and process correction (OPC) method for a mask that can be used for multiple exposure techniques. SOLUTION: In the method of optical process correction, mapping does not necessarily provide a one-to-one correspondence between reticle fragments and target layout fragments. That is, multiple reticle layout fragments can be mapped to a single target layout fragment. An edge placement error for the target layout fragments is used to make positioning corrections for the corresponding reticle fragments. The edge placement error can be determined, for example, with a simulation process that simulates a manufacturing process using the reticle. COPYRIGHT: (C)2008,JPO&INPIT

10. 发明专利

JP2006343756A INTEGRATED VERIFICATION AND MANUFACTURABILITY TOOL 审中-公开
公开(公告)号：JP2006343756A
公开(公告)日：2006-12-21
申请号：JP2006161662
申请日：2006-06-09
申请人： MENTOR GRAPHICS CORP
发明人： ANDERSON LEIGH C , COBB NICOLAS B , GRODD LAURENCE W , SAHOURIA EMILE , YOU SIQIONG
IPC分类号： G03F1/08 , G01Q30/04 , G01Q60/00 , G01Q70/06 , G01Q80/00 , G03F1/00 , G06F17/50
摘要： PROBLEM TO BE SOLVED: To provide an integrated verification and manufacturability tool that provides more efficient verification of integrated device designs. SOLUTION: This verification uses several different verification tools. The integrated verification and manufacturability tool includes a hierarchical database to store design data accessed by a plurality of verification tool components (e.g., layout versus schematic 440, design rule check 450, optical process correction 430, and phase shift mask assignment 420). A checking component includes a layout versus schematic (LVS) component. COPYRIGHT: (C)2007,JPO&INPIT

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