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1. 发明申请

WO1995028032A1 TIMING GENERATOR 审中-公开
标题翻译：时间发生器
公开(公告)号：WO1995028032A1
公开(公告)日：1995-10-19
申请号：PCT/US1995004355
申请日：1995-04-06
申请人： MEDIA VISION, INC.
发明人： MEDIA VISION, INC. , COLVIN, Bryan, J. , SHINDO, Masao
IPC分类号： H03B05/00
CPC分类号： H03K3/0315 , H03B27/00 , H03L7/0995
摘要： A timing generator contains an oscillator section (10) formed with a plural number of stages (S1-SN) for respectively producing a like number of stage signals (VS1-VSN) that sequentially change signal values at a basic oscillator frequency (f0). The oscillator section is typically implemented as a ring oscillator. In response to the stage signals, a timing-signal generating section (14) generates one or more timing signals (VT1-VTM), each having at least two transitions corresponding to transitions of two or more of the stage signals. A control section (12), preferably arranged in a phase-locked loop; causes the oscillator frequency and a reference frequency (fR) to have a substantially fixed relationship.
摘要翻译：定时发生器包括形成有多个级（S1-SN）的振荡器部分（10），用于分别产生以基本振荡器频率（f0）顺序改变信号值的相同数量的级信号（VS1-VSN）。振荡器部分通常被实现为环形振荡器。响应于级信号，定时信号产生部分（14）产生一个或多个定时信号（VT1-VTM），每个定时信号具有对应于两个或更多个级信号的转变的至少两个转变。控制部分（12），优选地布置在锁相环中; 使振荡器频率和参考频率（fR）具有基本上固定的关系。

2. 发明申请

WO1995027939A1 MUSICAL INSTRUMENT SIMULATION PROCESSOR 审中-公开
标题翻译：音乐仪器模拟处理器
公开(公告)号：WO1995027939A1
公开(公告)日：1995-10-19
申请号：PCT/US1995004354
申请日：1995-04-06
申请人： MEDIA VISION, INC.
发明人： MEDIA VISION, INC. , COLVIN, Bryan, J., Sr. , GOCHNAUER, Daniel, B. , COOK, Perry, R.
IPC分类号： G06F07/38
CPC分类号： G10H7/004 , G06F15/7857 , G10H2250/211
摘要： A self-contained fully programmable digital signal processor (100) has two processors (101, 102) sharing, in parallel interleave fashion, a math unit (103) such as a multiply-and-accumulate circuit. A background processor (102) controls an external dram and preprocesses the information for a foreground processor (101). On-chip sram (107, 110) stores program parameters for both the foreground and background processors and facilitate information transfer between the foreground and background processors. The sram is time-multiplexed to permit access by the foreground processor, the background processor, and external devices without the expense of multiport sram. Flip-flops maintain data signals to the math unit while the sram is being accessed. The foreground processor has a custom instruction set that optimizes the implementation of complex music synthesis filter structures. An on-chip white noise generator quickly provides pseudorandom data for some of the instructions.
摘要翻译：独立的完全可编程数字信号处理器（100）具有以并行交错方式共享诸如乘法和累加电路的数学单元（103）的两个处理器（101,102）。背景处理器（102）控制外部电视并预处理前景处理器（101）的信息。片上sram（107,110）存储前台和后台处理器的程序参数，并促进前台和后台处理器之间的信息传输。 sram被时分复用以允许前台处理器，后台处理器和外部设备的访问，而不需要多端口sram的费用。触发器在访问sram时将数据信号保留到数学单元。前台处理器具有自定义指令集，可以优化复杂音乐合成滤波器结构的实现。片上白噪声发生器可以快速提供某些指令的伪随机数据。

3. 发明申请

WO1995006859A1 RESIDUAL EXCITED WAVE GUIDE 审中-公开
标题翻译：残余波导指南
公开(公告)号：WO1995006859A1
公开(公告)日：1995-03-09
申请号：PCT/US1994009887
申请日：1994-09-01
申请人： MEDIA VISION, INC.
发明人： MEDIA VISION, INC. , COLVIN, Bryan, J., Sr. , COOK, Perry, R. , GOCHNAUER, Daniel
IPC分类号： G01H01/12
CPC分类号： G10H1/057 , G10H1/125
摘要： Synthesizer models for emulating musical instruments can be improved using an analysis model that compares the output signal (Y') of the model to a recording (S) of a desired sound and derives a residual signal (delta) that can be used to correct the model. When the original model is a good one, the residual signal is small and takes much less memory to store than is required for a sampled sound.
摘要翻译：可以使用将模型的输出信号（Y'）与期望声音的记录（S）进行比较的分析模型来改进用于模拟乐器的合成器模型，并且导出可用于校正乐谱的残差信号（delta）模型。当原始模型是好的时候，剩余信号很小，并且比采样声音需要的存储空间要少得多。

4. 发明申请

WO1996015584A1 IMPROVED DIGITAL SYNTHESIZER 审中-公开
标题翻译：改进的数字合成器
公开(公告)号：WO1996015584A1
公开(公告)日：1996-05-23
申请号：PCT/US1995014953
申请日：1995-11-14
申请人： MEDIA VISION, INC. , COOK, Perry , SHINDO, Masao
发明人： MEDIA VISION, INC.
IPC分类号： H03B21/00
CPC分类号： H03B21/00 , G06F1/0335 , H03C1/00
摘要： An improved apparatus for digitally synthesizing musical sounds. The apparatus according to the invention includes a phase angle generator (28), a quarterwave sine logic element (30), a wave constructor component (34) and a modulation logic component (38). A phase angle signal value from the phase angle generator (28) is output to the quarterwave sine logic component (30), and the circuit components are multiplexed to provide repeated signal generation steps to ultimately create a digitally synthesized musical sound output.
摘要翻译：一种用于数字合成音乐声音的改进装置。根据本发明的装置包括相位角发生器（28），四分之一波长正弦逻辑元件（30），波形构造器部件（34）和调制逻辑部件（38）。来自相位角发生器（28）的相位角信号值被输出到四分之一波长正弦逻辑分量（30），并且电路分量被多路复用以提供重复的信号产生步骤，以最终产生数字合成的音乐声输出。

5. 发明申请

WO1995027940A1 ECONOMICAL GENERATION OF EXPONENTIAL AND PSEUDO-EXPONENTIAL DECAY FUNCTIONS IN DIGITAL HARDWARE 审中-公开
标题翻译：数字硬件中的经典和伪指数衰减函数的经济生成
公开(公告)号：WO1995027940A1
公开(公告)日：1995-10-19
申请号：PCT/US1995004356
申请日：1995-04-06
申请人： MEDIA VISION, INC.
发明人： MEDIA VISION, INC. , COOK, Perry, R. , COLVIN, Bryan, J., Sr.
IPC分类号： G06F07/556
CPC分类号： G06F7/556 , G10H1/0575 , G10H7/12
摘要： Exponential and pseudo-exponential decay function values are generated by scaling a fractional decrease per sampling period by a previous decay function value and then subtracting the scaled fractional decrease from the previous decay function value. In one embodiment, a multiplier multiplies the fractional decrease by the previous decay function value and provides a product signal representing the scaled fractional decrease. An adder subtracts the scaled fractional decrease from the previous decay function value. In another embodiment, a shift block replaces the multiplier and approximates multiplication by a binary shift of the fractional decrease. The size of the shift is determined by the previous magnitude of the decay function as indicated by a priority encoder. Shifting generates a pseudo-exponential decay function which is suitable for music synthesis and can be generated quickly using less expensive hardware.
摘要翻译：指数和伪指数衰减函数值是通过以前一个衰减函数值缩放每个采样周期的分数下降，然后从前一个衰减函数值中减去缩放的分数下降来生成的。在一个实施例中，乘法器将分数减小乘以先前衰减函数值，并提供表示缩放分数下降的乘积信号。加法器从前一个衰减函数值中减去缩放的分数下降。在另一个实施例中，移位块代替乘法器并通过分数减小的二进制移位近似乘法。移位的大小由优先级编码器指示的衰减函数的先前幅度确定。移位产生适合于音乐合成的伪指数衰减函数，可以使用较便宜的硬件快速生成。

6. 发明申请

WO1993017395A1 DIGITALLY CONTROLLED INTEGRATED CIRCUIT ANTI-CLIPPING MIXER 审中-公开
标题翻译：数字控制集成电路防夹机
公开(公告)号：WO1993017395A1
公开(公告)日：1993-09-02
申请号：PCT/US1993001522
申请日：1993-02-22
申请人： MEDIA VISION, INC.
发明人： MEDIA VISION, INC. , COLVIN, Bryan, J., Sr.
IPC分类号： G06G07/16
CPC分类号： H03G7/005
摘要： An anti-clipping mixer circuit is provided within an integrated circuit. The mixer circuit allows for the independent level control of each input signal (IN(1), IN(i)), thereby allowing the optimization of the signal-to-noise ratio. A master level control is provided to limit the overall combined output signal to a level below the operational amplifier's (10) maximum voltage level. A control circuit (16) may be used to automatically adjust the input signal levels as well as the combined output signal level.

7. 发明申请

WO1995006936A1 SOUND SYNTHESIS MODEL INCORPORATING SYMPATHETIC VIBRATIONS OF STRINGS 审中-公开
标题翻译：声音合成模型包含声带的同步振动
公开(公告)号：WO1995006936A1
公开(公告)日：1995-03-09
申请号：PCT/US1994009892
申请日：1994-09-01
申请人： MEDIA VISION, INC.
发明人： MEDIA VISION, INC. , COLVIN, Bryan, J., Sr. , COOK, Perry, R.
IPC分类号： G10H01/02
CPC分类号： G10H5/007 , G10H2210/271 , G10H2250/441 , G10H2250/521
摘要： Synthesizer models for emulating musical instruments are improved to take into account sympathetic string vibrations. One embodiment of the present invention scales an output signal from a sound synthesis model (220) and uses the scaled signal as an input signal for a number of single-string emulators (201-212) causing the single-string emulators to produce sound signals corresponding to sympathetic string vibrations. The output signals from the synthesis model (220) and from all of the single-string emulators (201-212) are added together. Another embodiment employs an octave's worth of single-string emulators to emulate the lower strings of an emulated instrument. Still another embodiment is a synthesizer which includes an input bus (220A) for accepting a sound signal, scaling means (244), a plurality of single-string emulators, and means for summing output signals from the string emulators. Embodiments preferably employ waveguide synthesis or the plucked string model to emulate single strings.
摘要翻译：用于仿真乐器的合成器模型得到改进，以考虑到同情弦的振动。本发明的一个实施例对来自声音合成模型（220）的输出信号进行缩放，并且将缩放的信号用作多个单串模拟器（201-212）的输入信号，从而使单串模拟器产生声音信号对应于交感神经刺激。来自合成模型（220）和所有单串模拟器（201-212）的输出信号被加在一起。另一个实施例使用八度音阶的单串仿真器来模拟仿真乐器的较低弦。另一个实施例是一种合成器，其包括用于接收声音信号的输入总线（220A），缩放装置（244），多个单串仿真器，以及用于对来自串式仿真器的输出信号求和的装置。实施例优选地采用波导合成或采摘串模型来模拟单个串。

8. 发明申请

WO1994001928A1 AUDIO POWER AMPLIFIER WITH NOISE PREVENTION AT TURN-ON AND TURN-OFF 审中-公开
标题翻译：音频功率放大器，带有噪音防止在开启和关闭
公开(公告)号：WO1994001928A1
公开(公告)日：1994-01-20
申请号：PCT/US1993006389
申请日：1993-07-09
申请人： MEDIA VISION, INC.
发明人： MEDIA VISION, INC. , ROVNER, Michael, Scott , COLVIN, Bryan, Joseph, Sr.
IPC分类号： H03F01/26
CPC分类号： H03F1/305
摘要： An audio power amplifier (10, 20) is provided that includes circuitry to prevent popping noises when the amplifier is turned on and turned off. The amplifier can be powered with a single-ended voltage power supply, and thus may be used within systems such as personal computers. The amplifier includes a control circuit (50) that prevents the fast charging of the output AC coupling capacitor (16) when the amplifier is turned on and turned off. The control circuit controls a driver stage (20) such that the output transistors (12, 14) turn on slowly when power is first applied, and such that the output transistors turn off quickly when the supply voltage is removed.
摘要翻译：提供了一种音频功率放大器（10,20），其包括当放大器接通和断开时防止爆震噪声的电路。放大器可以使用单端电压电源供电，因此可以在诸如个人计算机的系统内使用。放大器包括控制电路（50），当放大器接通和断开时，该控制电路防止输出AC耦合电容器（16）的快速充电。控制电路控制驱动器级（20），使得当第一次施加电力时，输出晶体管（12,14）缓慢地导通，并且使得输出晶体管在电源电压被去除时快速关断。

9. 发明申请

WO1994000949A1 VIDEO COMPRESSION AND DECOMPRESSION USING BLOCK SELECTION AND SUBDIVISION 审中-公开
标题翻译：使用块选择和分割的视频压缩和分解
公开(公告)号：WO1994000949A1
公开(公告)日：1994-01-06
申请号：PCT/US1993005671
申请日：1993-06-18
申请人： MEDIA VISION, INC.
发明人： MEDIA VISION, INC. , RAFFERTY, James, W.
IPC分类号： H04N01/415
CPC分类号： H04N1/64 , H04N19/13 , H04N19/60 , H04N19/91 , H04N19/98
摘要： A frame (1) of digitized video data is compressed by dividing the frame into a plurality of rectangular blocks (2-5) each typically measuring 4 pixels by 4 pixels. The entropy of each block is determined by measuring the difference between a maximum luminance of any pixel in the block and the minimum luminance of any pixel in the block. Those blocks which have a luminance value above a predetermined threshold (70) (such as the average luminance for the block) are then subdivided into four blocks each including four pixels. Then, for each sub-block of 4 pixels a conventional video color compression technique is applied. For the non-subdivided blocks i.e., where the maximum luminance difference is below the threshold, the entire block is video compressed into a high color value and a low color value which are typically averages of the higher luminance and lower luminance group pixels respectively.
摘要翻译：通过将帧划分成多个矩形块（2-5）来压缩数字化视频数据的帧（1），每个矩形块通常测量4像素乘4像素。通过测量块中任何像素的最大亮度与块中的任何像素的最小亮度之间的差来确定每个块的熵。然后将具有高于预定阈值（70）的亮度值（诸如块的平均亮度）的那些块细分为四个包括四个像素的块。然后，对于4像素的每个子块，应用传统的视频彩色压缩技术。对于非细分块，即最大亮度差低于阈值，整个块被视频压缩成分别是较高亮度和较低亮度组像素的典型平均值的高色值和低色值。

10. 发明申请

WO1993017497A1 CIRCUIT FOR FILTERING ASYNCHRONOUS METASTABILITY OF CROSS-COUPLED LOGIC GATES 审中-公开
标题翻译：用于过滤耦合逻辑门的异步可调性电路
公开(公告)号：WO1993017497A1
公开(公告)日：1993-09-02
申请号：PCT/US1993001536
申请日：1993-02-22
申请人： MEDIA VISION, INC.
发明人： MEDIA VISION, INC. , COLVIN, Bryan, J., Sr.
IPC分类号： H03K03/286
CPC分类号： H03K19/21 , H03K3/0375
摘要： A circuit is provided for filtering asynchronous metastability. The circuit includes two or more output lines (30, 32) that provide signals indicative of the assertion of control or data input signals at a plurality of input lines (26, 28). Despite the simultaneous assertion of two more more input signals, the circuit prevents the simultaneous assertion of more than one output signal, thereby preventing adverse effects within a digital system connected to the circuit.
摘要翻译：提供了一种用于过滤异步亚稳态的电路。电路包括两个或多个输出线（30,32），其提供指示在多个输入线（26,28）上断言控制或数据输入信号的信号。尽管同时断言两个以上输入信号，该电路防止同时断言多于一个输出信号，从而防止连接到电路的数字系统内的不利影响。

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