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    • 1. 发明申请
    • METHOD OF ETCHING FEATURES INTO SUBSTRATE
    • 将特征浸入底层的方法
    • WO2011066668A1
    • 2011-06-09
    • PCT/CN2009/001358
    • 2009-12-02
    • MCREYNOLDS, Darrell, LarueC SUN MFG. LTD.
    • MCREYNOLDS, Darrell, Larue
    • H01L21/3065C23F1/12
    • H01L21/3065
    • A method of etching a substrate, such as silicon, using a plasma reactor to form deep features is provided. The method includes the steps of putting a semiconductor substrate including, but not limited to a silicon layer, into a plasma reactor, and flowing an etching gas that includes fluorinated etching gas, passivating reacting gas comprising oxygen and inert sputtering gas. An additional gas can be added, but not necessarily, such as nitrogen, carbon monoxide, CFx, CHFx, CxFy or hydrogen bromide, to assist in feature dimensional control. The feature dimensional control gas can control the feature size and etch angle. The method further promotes a silicon monoxide sidewall passivation to enhance feature dimensional control.
    • 提供了使用等离子体反应器来蚀刻诸如硅的衬底以形成深度特征的方法。 该方法包括以下步骤:将包括但不限于硅层的半导体衬底放入等离子体反应器中,并使包括氟化蚀刻气体的蚀刻气体,包含氧和惰性溅射气体的钝化反应气体流动。 可以添加另外的气体,但不一定如氮气,一氧化碳,CFx,CHFx,CxFy或溴化氢,以辅助特征尺寸控制。 特征尺寸控制气体可以控制特征尺寸和蚀刻角度。 该方法进一步促进一氧化硅侧壁钝化以增强特征尺寸控制。
    • 2. 发明申请
    • METHOD FOR FORMING VIA INTERCONNECTS FOR 3-D WAFER/CHIP STACKING
    • 通过三维波形/芯片堆叠互连形成的方法
    • WO2011063552A1
    • 2011-06-03
    • PCT/CN2009/001337
    • 2009-11-27
    • MCREYNOLDS, Darrell LarueC SUN MFG, LTD.
    • MCREYNOLDS, Darrell Larue
    • H01L21/768H01L21/3065
    • H01L21/76898H01L21/3065
    • A method for forming via interconnects in a silicon wafer comprises steps: forming a mask on a substrate; performing an etching step on the mask to form an opening; etching the substrate at the opening to form a via interconnect, the via interconnect has a sidewall, a bottom, and a depth; performing a chemical vapor deposition step with sulfur hexafluoride and oxygen for depositing an insulating oxide layer, the insulating oxide layer covers the sidewall and the bottom of the via interconnect and the mask; performing an ion bombardment gas etching step to etch the insulating oxide layer covered on the bottom of the via interconnect with an ion bombardment gas, the ion bombardment gas comprises at least one of the argon, boron, helium, nitrogen, and fluorocarbon; and performing a physical vapor deposition step to form a conductive material layer, the conductive material layer covers the sidewall and the bottom of the via interconnect and the mask.
    • 用于在硅晶片中形成通孔互连的方法包括以下步骤:在衬底上形成掩模; 在掩模上进行蚀刻步骤以形成开口; 在开口处蚀刻基板以形成通孔互连,通孔互连具有侧壁,底部和深度; 用六氟化硫和氧气进行化学气相沉积步骤,用于沉积绝缘氧化物层,绝缘氧化物层覆盖通路互连和掩模的侧壁和底部; 进行离子轰击气体蚀刻步骤以用离子轰击气体蚀刻通孔互连底部覆盖的绝缘氧化物层,所述离子轰击气体包括氩,硼,氦,氮和碳氟化合物中的至少一种; 并且进行物理气相沉积步骤以形成导电材料层,所述导电材料层覆盖所述通孔互连件和所述掩模的侧壁和底部。