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1. 发明专利

JP2016515252A ビデオストリーム解析审中-公开
标题翻译：视频流分析
公开(公告)号：JP2016515252A
公开(公告)日：2016-05-26
申请号：JP2015562087
申请日：2014-03-11
申请人：マーティンフォアバッハMartin Vorbach , マーティンフォアバッハMartin Vorbach
发明人：レナーアレクサンダー , レナーアレクサンダー
IPC分类号： G06T7/20 , H04N5/232
CPC分类号： G06K9/00771 , G06K9/00711 , G06K9/00744 , G06T7/0004 , G06T7/254 , G06T7/269 , G06T2207/30232 , H04N7/18 , H04N17/004
摘要：本発明は、ビデオストリームで取得された行動を認識する方法に関する。前記方法では、各フレームシーケンスについてフィールドに、フレーム間差分に関するデータを累積し、当該累積部フィールドにおける勾配および/または値差分間隔を求め、当該勾配から行動を推定する。
摘要翻译：本发明涉及用于识别视频流中获取的动作的方法。在该方法中，对于每个帧序列的场，累积与所述帧间差值数据，确定在蓄能器领域的斜率和/或值的差的时间间隔，来估计梯度的行为。

2. 发明专利

GB2549883A Advanced processor architecture 未知
公开(公告)号：GB2549883A
公开(公告)日：2017-11-01
申请号：GB201711202
申请日：2015-12-13
申请人： HYPERION CORE INC , MARTIN VORBACH
发明人： MARTIN VORBACH
IPC分类号： G06F9/38
摘要： The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises : 1) looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly; 2) checking for an Execution Unit (EXU) available for receiving a new instruction; and 3) issuing the instruction to the available Execution Unit and enter a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).

3. 发明授权

US11061682B2 Advanced processor architecture 有权
公开(公告)号：US11061682B2
公开(公告)日：2021-07-13
申请号：US15535697
申请日：2015-12-13
申请人： Martin Vorbach , Hyperion Core, Inc.
发明人： Martin Vorbach
IPC分类号： G06F9/38 , G06F9/30 , G06F9/32
摘要： The invention relates to a method for processing instructions out-of-order on a processor comprising an arrangement of execution units. The inventive method comprises looking up operand sources in a Register Positioning Table and setting operand input references of the instruction to be issued accordingly, checking for an Execution Unit (EXU) available for receiving a new instruction, and issuing the instruction to the available Execution Unit and entering a reference of the result register addressed by the instruction to be issued to the Execution Unit into the Register Positioning Table (RPT).

4. 发明授权

US09703538B2 Tool-level and hardware-level code optimization and respective hardware modification 有权
公开(公告)号：US09703538B2
公开(公告)日：2017-07-11
申请号：US14124636
申请日：2012-06-06
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F9/44 , G06F9/45 , G06F17/50
CPC分类号： G06F8/443 , G06F8/4434 , G06F8/447 , G06F17/504 , G06F17/5045 , G06F17/5054
摘要： The present invention relates to a method for compiling high-level software code into hardware, transforming each instruction into a respective hardware block and using an execution control signal representing the program pointer for triggering the execution within each respective hardware block.

5. 发明授权

US09348587B2 Providing code sections for matrix of arithmetic logic units in a processor 有权
标题翻译：为处理器中的算术逻辑单元的矩阵提供代码段
公开(公告)号：US09348587B2
公开(公告)日：2016-05-24
申请号：US13809159
申请日：2011-07-08
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F9/30 , G06F9/32 , G06F9/355 , G06F9/38
CPC分类号： G06F9/381 , G06F9/3001 , G06F9/30043 , G06F9/30054 , G06F9/30058 , G06F9/30065 , G06F9/30072 , G06F9/30076 , G06F9/30094 , G06F9/30098 , G06F9/3013 , G06F9/30138 , G06F9/30167 , G06F9/325 , G06F9/355 , G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3887 , G06F9/3889
摘要： The present invention relates to a processor having a trace cache and a plurality of ALUs arranged in a matrix, comprising an analyzer unit located between the trace cache and the ALUs, wherein the analyzer unit analyzes the code in the trace cache, detects loops, transforms the code, and issues to the ALUs sections of the code combined to blocks for joint execution for a plurality of clock cycles.
摘要翻译：本发明涉及具有跟踪高速缓存和排列成矩阵的多个ALU的处理器，包括位于跟踪高速缓存和ALU之间的分析器单元，其中分析器单元分析跟踪高速缓存中的代码，检测循环，变换所述代码和所述代码的ALU部分的组合结合到用于多个时钟周期的联合执行的块。

6. 发明授权

US09152427B2 Instruction issue to array of arithmetic cells coupled to load/store cells with associated registers as extended register file 有权
标题翻译：对与加载/存储单元相关联的算术单元的数组的指令问题与相关联的寄存器作为扩展寄存器文件
公开(公告)号：US09152427B2
公开(公告)日：2015-10-06
申请号：US13123527
申请日：2009-10-15
申请人： Martin Vorbach , Frank May , Markus Weinhardt
发明人： Martin Vorbach , Frank May , Markus Weinhardt
IPC分类号： G06F9/38 , G06F9/45 , G06F9/30
CPC分类号： G06F9/3836 , G06F8/443 , G06F9/3001 , G06F9/30043 , G06F9/30065 , G06F9/3012 , G06F9/30123 , G06F9/30134 , G06F9/30189 , G06F9/381 , G06F9/3859 , G06F9/3867 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
摘要翻译：本发明公开了一种单芯片顺序处理器，其包括至少一个ALU块，其中所述顺序处理器能够在处理数据时保持其操作码，以克服在每个时钟周期中需要新指令的必要性。

7. 发明授权

US08914590B2 Data processing method and device 有权
标题翻译：数据处理方法和装置
公开(公告)号：US08914590B2
公开(公告)日：2014-12-16
申请号：US12570943
申请日：2009-09-30
申请人： Martin Vorbach , Jürgen Becker , Markus Weinhardt , Volker Baumgarte , Frank May
发明人： Martin Vorbach , Jürgen Becker , Markus Weinhardt , Volker Baumgarte , Frank May
IPC分类号： G06F12/00 , G06F15/78 , G06F12/08 , G06F9/30 , G06F9/345 , G06F9/38
CPC分类号： G06F15/7814 , G06F9/30047 , G06F9/30076 , G06F9/3455 , G06F9/3897 , G06F12/0862
摘要： In a data-processing method, first result data may be obtained using a plurality of configurable coarse-granular elements, the first result data may be written into a memory that includes spatially separate first and second memory areas and that is connected via a bus to the plurality of configurable coarse-granular elements, the first result data may be subsequently read out from the memory, and the first result data may be subsequently processed using the plurality of configurable coarse-granular elements. In a first configuration, the first memory area may be configured as a write memory, and the second memory area may be configured as a read memory. Subsequent to writing to and reading from the memory in accordance with the first configuration, the first memory area may be configured as a read memory, and the second memory area may be configured as a write memory.
摘要翻译：在数据处理方法中，可以使用多个可配置的粗粒度元素来获得第一结果数据，第一结果数据可以被写入到包括空间上分离的第一和第二存储器区域并且经由总线连接到可以随后从存储器中读出多个可配置的粗粒度元素，第一结果数据可以随后使用多个可配置的粗粒度元素进行处理。在第一配置中，第一存储器区域可以被配置为写入存储器，并且第二存储器区域可以被配置为读取存储器。在根据第一配置写入和读取存储器之后，第一存储器区域可以被配置为读取存储器，并且第二存储器区域可以被配置为写入存储器。

8. 发明申请

US20140143509A1 METHOD AND DEVICE FOR DATA PROCESSING 审中-公开
标题翻译：用于数据处理的方法和装置
公开(公告)号：US20140143509A1
公开(公告)日：2014-05-22
申请号：US14162704
申请日：2014-01-23
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F3/06
CPC分类号： G06F8/447
摘要： The present provides a method for operating a module by a processor. The method includes generating, by at least one task being executed on the processor, control information for controlling operation of the module. The module includes an arrangement of a plurality of cells, including a bus system. At least some of the cells having arithmetic and logic units. At least some of the cells being arranged in at least two dimensions. The method further including writing, by the processor, the control information into a memory being shared with the module in a list-like manner to form a list of operations. The method further including executing, by the module, the operations listed in the list.
摘要翻译：本发明提供了一种由处理器操作模块的方法。该方法包括通过在处理器上执行的至少一个任务生成用于控制模块的操作的控制信息。该模块包括多个单元的布置，包括总线系统。至少一些具有算术和逻辑单元的单元。至少一些单元被布置在至少两个维度中。该方法还包括由处理器将控制信息以类似列表的方式写入与模块共享的存储器中，以形成操作列表。该方法还包括由模块执行列表中列出的操作。

9. 发明授权

US08407525B2 Method for debugging reconfigurable architectures 有权
公开(公告)号：US08407525B2
公开(公告)日：2013-03-26
申请号：US13279561
申请日：2011-10-24
申请人： Martin Vorbach
发明人： Martin Vorbach
IPC分类号： G06F11/00
CPC分类号： G06F11/26 , G06F9/30036 , G06F11/267 , G06F11/3656 , G06F15/7867
摘要： A method for debugging reconfigurable hardware is described. According to this method, all necessary debug information is written in each configuration cycle into a memory, which is then analyzed by the debugger.

10. 发明申请

US20120216012A1 SEQUENTIAL PROCESSOR COMPRISING AN ALU ARRAY 有权
标题翻译：包含ALU阵列的顺序处理器
公开(公告)号：US20120216012A1
公开(公告)日：2012-08-23
申请号：US13123527
申请日：2009-10-15
申请人： Martin Vorbach , Frank May , Markus Weinhardt
发明人： Martin Vorbach , Frank May , Markus Weinhardt
IPC分类号： G06F15/80 , G06F9/06
CPC分类号： G06F9/3836 , G06F8/443 , G06F9/3001 , G06F9/30043 , G06F9/30065 , G06F9/3012 , G06F9/30123 , G06F9/30134 , G06F9/30189 , G06F9/381 , G06F9/3859 , G06F9/3867 , G06F9/3885 , G06F9/3887 , G06F9/3889
摘要： The present invention discloses a single chip sequential processor comprising at least one ALU-Block wherein said sequential processor is capable of maintaining its op-codes while processing data such as to overcome the necessity of requiring a new instruction in every clock cycle.
摘要翻译：本发明公开了一种单芯片顺序处理器，其包括至少一个ALU块，其中所述顺序处理器能够在处理数据时保持其操作码，以克服在每个时钟周期中需要新指令的必要性。

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