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1. 发明授权

US06452789B1 Packaging architecture for 32 processor server 有权
标题翻译： 32处理器服务器的包装架构
公开(公告)号：US06452789B1
公开(公告)日：2002-09-17
申请号：US09562593
申请日：2000-04-29
申请人： Lisa Heid Pallotti , Eric C. Peterson , Christian L Belady , Terrel L. Morris , Michael C. Day
发明人： Lisa Heid Pallotti , Eric C. Peterson , Christian L Belady , Terrel L. Morris , Michael C. Day
IPC分类号： G06F1200
CPC分类号： G06F15/16
摘要： The inventive system uses a backplane to interconnect a plurality of modular cell boards. Each cell board comprises a plurality of processors, a processor controller chip, a memory subsystem, and a power subsystem. The processor controller chip manages communications between components on the cell board. A mechanical subassembly provides support for the cell board, as well as ventilation passages for cooling. Controller chips are connected to one side of the backplane, while the cell boards are connected to the other side. The controller chips manage cell board to cell board communications, and communications between the backplane and the computer system. The cell boards are arranged in back to back pairs, with the outer most cell boards having their components extend beyond the height of the backplane. This allows for an increase of spacing between the front to front interface of adjacent cell boards.
摘要翻译：本发明的系统使用背板来互连多个模块化单元板。每个单元板包括多个处理器，处理器控制器芯片，存储器子系统和电源子系统。处理器控制器芯片管理单元板上的组件之间的通信。机械子组件为电池板提供支撑，以及用于冷却的通风通道。控制器芯片连接到背板的一侧，而单元板连接到另一侧。控制器芯片管理单元板到单元板通信，以及背板和计算机系统之间的通信。单元板布置成背靠背对，其中最外面的单元板具有其组件延伸超出背板的高度。这允许相邻电池板的前面与前面之间的间隔增加。

2. 发明授权

US06818835B2 Processor and power supply circuit 有权
标题翻译：处理器和电源电路
公开(公告)号：US06818835B2
公开(公告)日：2004-11-16
申请号：US10420572
申请日：2003-04-22
申请人： Stuart C. Haden , Shaun L. Harris , Michael C. Day , Christian L Belady , Lisa Heid Pallotti , Paul T. Artman , Eric C. Peterson
发明人： Stuart C. Haden , Shaun L. Harris , Michael C. Day , Christian L Belady , Lisa Heid Pallotti , Paul T. Artman , Eric C. Peterson
IPC分类号： H05K103
CPC分类号： H05K1/0231 , H05K1/0262 , H05K1/113 , H05K2201/09309 , H05K2201/0979 , H05K2201/10636 , Y02P70/611
摘要： A circuit comprising multiple circuit boards is disclosed herein. An embodiment of the circuit may comprise first and second printed circuit boards. The first printed circuit board may comprise first and second conductive planes. The first conductive plane has a first shape and the second conductive plane has a second shape, wherein the first shape is substantially similar to the second shape. The first conductive plane is located adjacent the second conductive plane, wherein the first conductive plane is parallel to and aligned with the second conductive plane. The second printed circuit board is connected to the first printed circuit board.
摘要翻译：本文公开了包括多个电路板的电路。电路的实施例可以包括第一和第二印刷电路板。第一印刷电路板可包括第一和第二导电平面。第一导电平面具有第一形状，第二导电平面具有第二形状，其中第一形状基本上类似于第二形状。第一导电平面位于第二导电平面附近，其中第一导电平面平行于第二导电平面并与第二导电平面对准。第二印刷电路板连接到第一印刷电路板。

3. 发明授权

US07206889B2 Systems and methods for enabling communications among devices in a multi-cache line size environment and disabling communications among devices of incompatible cache line sizes 失效
标题翻译：用于实现多高速缓存行大小环境中的设备之间的通信并禁用不兼容的高速缓存行大小的设备之间的通信的系统和方法
公开(公告)号：US07206889B2
公开(公告)日：2007-04-17
申请号：US11085883
申请日：2005-03-22
申请人： Mark E. Shaw , Gary B. Gostin , Lisa Heid Pallotti
发明人： Mark E. Shaw , Gary B. Gostin , Lisa Heid Pallotti
IPC分类号： G06F12/00 , G06F13/00 , G06F13/16
CPC分类号： G06F13/4022 , G06F12/0886 , G06F2212/601
摘要： A system and method for facilitating communications between a plurality of devices that communicate using different cache-line sizes are disclosed. Briefly described, in architecture, one exemplary embodiment of a compatible cache-line communication system employs a plurality of first ports, each first port configured to receive communications from a first type of device that uses a first cache-line size; and a plurality of second ports, each second port configured to receive communications from a second type of device that uses a second cache-line size, such that communications between the first type of devices are enabled over a plurality of first routes, such that communications between the second type of devices are enabled over a plurality of second routes, and such that communications between the first type of devices and the second type of devices are disabled.
摘要翻译：公开了一种用于促进使用不同高速缓存行大小进行通信的多个设备之间的通信的系统和方法。简要描述，在架构中，兼容高速缓存行通信系统的一个示例性实施例采用多个第一端口，每个第一端口被配置为从使用第一高速缓存行大小的第一类型的设备接收通信; 以及多个第二端口，每个第二端口被配置为从使用第二高速缓存行大小的第二类型的设备接收通信，使得第一类型的设备之间的通信在多个第一路由上被启用，使得通信在第二类型的设备之间通过多个第二路由启用，并且使得第一类型的设备和第二类型的设备之间的通信被禁用。

4. 发明授权

US06596948B1 Processor and power supply circuit 失效
标题翻译：处理器和电源电路
公开(公告)号：US06596948B1
公开(公告)日：2003-07-22
申请号：US09560794
申请日：2000-04-28
申请人： Stuart C. Haden , Shaun L. Harris , Michael C. Day , Lisa Heid Pallotti
发明人： Stuart C. Haden , Shaun L. Harris , Michael C. Day , Lisa Heid Pallotti
IPC分类号： H01R1204
CPC分类号： H05K1/0231 , H05K1/0262 , H05K1/113 , H05K2201/09309 , H05K2201/0979 , H05K2201/10636 , Y02P70/611
摘要： A high performance processor assembly is electrically connected to a power supply so as to minimize voltage variations associated with the supply of power to the processor assembly. The processor assembly is fabricated on a multilayered printed circuit board. Power is supplied to components on the printed circuit board by way of parallel and split power planes. The parallel and split power planes reduce inductance and increase capacitance associated therewith. The reduced inductance reduces voltage variations caused by load transient currents. Capacitors are electrically connected to the power planes by way of multiple vias to further reduce inductance.
摘要翻译：高性能处理器组件电连接到电源，以便最小化与向处理器组件供电的电压变化相关联。处理器组件制造在多层印刷电路板上。电源通过并联和分离电源平面提供给印刷电路板上的组件。并联和分离电源平面减小电感并增加与其相关联的电容。减小的电感降低了由负载瞬态电流引起的电压变化。电容器通过多个通孔电连接到电源层，以进一步降低电感。

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