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1. 发明授权

US07153780B2 Method and apparatus for self-aligned MOS patterning 失效
标题翻译：用于自对准MOS图案化的方法和装置
公开(公告)号：US07153780B2
公开(公告)日：2006-12-26
申请号：US10808793
申请日：2004-03-24
申请人： Ervin T. Hill , Oleh P. Karpenko , Gordon T. McGarvey , Linda N. Marquez
发明人： Ervin T. Hill , Oleh P. Karpenko , Gordon T. McGarvey , Linda N. Marquez
IPC分类号： H01L21/302
CPC分类号： H01L21/31144 , H01L21/28123 , H01L21/28273 , H01L21/32139
摘要： A method of forming a thin film stack on a substrate, wherein the thin film stack includes at least a polysilicon layer and an oxide layer; forming a hardmask layer on the thin film stack; forming an anti-reflective coating (ARC) layer on the hardmask layer; patterning the ARC layer; etching the hardmask layer using the patterned ARC layer as a mask; and etching the thin film stack using the hardmask layer as a mask.
摘要翻译：一种在衬底上形成薄膜堆叠的方法，其中所述薄膜叠层至少包括多晶硅层和氧化物层; 在所述薄膜叠层上形成硬掩模层; 在所述硬掩模层上形成抗反射涂层（ARC）层; 图案化ARC层; 使用图案化的ARC层作为掩模蚀刻硬掩模层; 并使用硬掩模层作为掩模蚀刻薄膜堆叠。

2. 发明授权

US06228774B1 High aspect ratio sub-micron contact etch process in an inductively-coupled plasma processing system 失效
标题翻译：电感耦合等离子体处理系统中的高纵横比亚微米接触蚀刻工艺
公开(公告)号：US06228774B1
公开(公告)日：2001-05-08
申请号：US09222551
申请日：1998-12-29
申请人： Linda N. Marquez
发明人： Linda N. Marquez
IPC分类号： H01L2100
CPC分类号： H01L21/31116 , H01L21/76802
摘要： The invention relates to a method of etching a feature in an oxide layer using a photoresist mask, the oxide layer being disposed above an underlying layer of a substrate inside an inductively-coupled plasma processing chamber. The method includes flowing an etchant source gas that includes CH2F2,C4F8 and O2 or C3H3F5,C4F8 and O2 into the plasma processing chamber. The method further includes forming a plasma from the etchant source gas. The method additionally includes etching through the oxide layer of the substrate with the plasma, wherein the etching substantially stops on the underlying layer, the underlying being one of a silicon layer, a tungsten-based layer or a TiN layer.
摘要翻译：本发明涉及一种使用光致抗蚀剂掩模蚀刻氧化物层中的特征的方法，该氧化物层设置在电感耦合等离子体处理室内部的基底的下方之上。该方法包括将包括CH 2 F 2，C 4 F 8和O 2或C 3 H 3 F 5，C 4 F 8和O 2的蚀刻剂源气体流入等离子体处理室。该方法还包括从蚀刻剂源气体形成等离子体。该方法另外包括用等离子体蚀刻穿过衬底的氧化物层，其中蚀刻基本上停留在下层上，下面是硅层，钨基层或TiN层之一。

3. 发明授权

US5783496A Methods and apparatus for etching self-aligned contacts 失效
标题翻译：蚀刻自对准触点的方法和装置
公开(公告)号：US5783496A
公开(公告)日：1998-07-21
申请号：US623526
申请日：1996-03-29
申请人： Janet M. Flanner , Prashant Gadgil , Linda N. Marquez , Adrian Doe , Joel M. Cook
发明人： Janet M. Flanner , Prashant Gadgil , Linda N. Marquez , Adrian Doe , Joel M. Cook
IPC分类号： H01L21/311 , H01L21/60 , H01L21/00
CPC分类号： H01L21/76897 , H01L21/31116
摘要： A method in a plasma processing chamber for fabricating a semiconductor device having a self-aligned contact. The method includes the step of providing a wafer having a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above a polysilicon layer, and an oxide layer disposed above the nitride layer. The method further includes the step of etching in a first etching step partially through the oxide layer of the layer stack with a first chemistry and a first set of process parameters. In this first etching step, the first chemistry comprises essentially of CHF.sub.3 and C.sub.2 HF.sub.5. The method also includes the step of etching the oxide layer in a second etching step through to the substrate with a second chemistry comprising CHF.sub.3 and C.sub.2 HF.sub.5 and a second set of process parameters. The second set of process parameters is different from the first set of process parameters and represents a set of parameters for etching the oxide layer with a higher oxide-to-nitride selectivity than the oxide-to-nitride selectivity achieved in the first etching step.
摘要翻译：一种用于制造具有自对准接触的半导体器件的等离子体处理室中的方法。该方法包括提供具有基板，设置在基板上方的多晶硅层，设置在多晶硅层上方的氮化物层和设置在氮化物层上方的氧化物层的晶片的步骤。该方法还包括在第一蚀刻步骤中通过第一化学和第一组工艺参数部分地蚀刻层堆叠的氧化物层的步骤。在该第一蚀刻步骤中，第一化学性质基本上由CHF 3和C 2 HF 5组成。该方法还包括在第二蚀刻步骤中通过具有包含CHF 3和C 2 HF 5的第二化学物质和第二组工艺参数在衬底中蚀刻氧化物层的步骤。第二组工艺参数与第一组工艺参数不同，并且表示用于蚀刻具有比在第一蚀刻步骤中实现的氧化物到氮化物选择性更高的氧化物到氮化物选择性的氧化物层的一组参数。

4. 发明授权

US06165910A Self-aligned contacts for semiconductor device 失效
标题翻译：用于半导体器件的自对准触点
公开(公告)号：US06165910A
公开(公告)日：2000-12-26
申请号：US998954
申请日：1997-12-29
申请人： Janet M. Flanner , Linda N. Marquez , Joel M. Cook , Ian J. Morey
发明人： Janet M. Flanner , Linda N. Marquez , Joel M. Cook , Ian J. Morey
IPC分类号： H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/3213 , H01L21/60 , H01L21/00
CPC分类号： H01L21/76897 , H01L21/31116
摘要： In a plasma processing chamber, a method for etching through a selected portion of an oxide layer of a wafer's layer stack to create a self-aligned contact opening is described. The wafer stack includes a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above said polysilicon layer and the oxide layer disposed above the nitride layer. The method for etching includes etching through the oxide layer of the layer stack with a chemistry and a set of process parameters. The chemistry essentially includes C.sub.2 HF.sub.5 and CH.sub.2 F.sub.2 and the set of process parameters facilitate etching through the oxide layer without creating a spiked etch and etching the oxide layer through to the substrate without substantially damaging the nitride layer.
摘要翻译：在等离子体处理室中，描述了通过晶片层叠层的氧化物层的选定部分蚀刻以形成自对准接触开口的方法。晶片堆叠包括基板，设置在基板上方的多晶硅层，设置在所述多晶硅层上方的氮化物层和设置在氮化物层上方的氧化物层。蚀刻方法包括通过化学和一组工艺参数蚀刻通过层叠层的氧化物层。化学性质基本上包括C 2 H 5 O 5和CH 2 F 2，并且一组工艺参数有助于蚀刻通过氧化物层而不产生加标蚀刻，并将氧化物层蚀刻到衬底上而不会基本上损坏氮化物层。

5. 发明授权

US6133153A Self-aligned contacts for semiconductor device 失效
标题翻译：用于半导体器件的自对准触点
公开(公告)号：US6133153A
公开(公告)日：2000-10-17
申请号：US52276
申请日：1998-03-30
申请人： Linda N. Marquez , Janet M. Flanner
发明人： Linda N. Marquez , Janet M. Flanner
IPC分类号： H01L21/28 , H01L21/302 , H01L21/3065 , H01L21/311 , H01L21/336 , H01L21/60 , H01L21/768 , H01L29/78
CPC分类号： H01L21/76897 , H01L21/31116
摘要： A plasma, formed from a mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2, is used to etch a self-aligned contact, the self-aligned contact being an opening in the oxide layer, the opening being aligned with an opening in an underlying nitride layer and extending to a substrate underlying the nitride. The mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2 provides a high ratio of oxide etch rate to nitride etch rate so that the etching is completed without substantially damaging the nitride layer. For thicker oxide layers a preliminary etch step using C.sub.2 F.sub.6 and C.sub.2 HF.sub.5 may be performed prior to using the mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2.
摘要翻译：使用由C 4 F 8和CH 2 F 2的混合物形成的等离子体来蚀刻自对准接触，该自对准接触是氧化物层中的开口，该开口与下面的氮化物层中的开口对准并延伸至氮化物下面的衬底。 C4F8和CH2F2的混合物提供高的氧化物蚀刻速率与氮化物蚀刻速率的比率，使得蚀刻完成而基本上不损害氮化物层。对于较厚的氧化物层，可以在使用C 4 F 8和CH 2 F 2的混合物之前进行使用C2F6和C2HF5的初步蚀刻步骤。

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