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1. 发明申请

US20130142190A1 Synchronization Channel Interference Cancellation 有权
标题翻译：同步信道干扰消除
公开(公告)号：US20130142190A1
公开(公告)日：2013-06-06
申请号：US13428022
申请日：2012-03-23
申请人： Hongwei Kong , Wei Luo , Li Fung Chang
发明人： Hongwei Kong , Wei Luo , Li Fung Chang
IPC分类号： H04W56/00
CPC分类号： H04W56/002 , H03M13/3723 , H03M13/3905 , H03M13/3972 , H04L1/005 , H04W36/18
摘要： Disclosed are various embodiments for cancellation of a PSCH signal and/or SSCH signal from an RX input signal. A PSCH sequence and SSCH sequence are extracted a PSCH and SSCH signal. A relative gain associated with the PSCH signal and SSCH signal are determined relative to a CPICH signal. A reconstructed PSCH and SSCH signal are generated and cancelled from the RX input signal.
摘要翻译：公开了用于从RX输入信号消除PSCH信号和/或SSCH信号的各种实施例。 PSCH序列和SSCH序列被提取出PSCH和SSCH信号。相对于CPICH信号确定与PSCH信号和SSCH信号相关联的相对增益。从RX输入信号产生并取消重构的PSCH和SSCH信号。

2. 发明授权

US08266509B2 Edge incremental redundancy memory structure and memory management 有权
标题翻译：边增量冗余内存结构和内存管理
公开(公告)号：US08266509B2
公开(公告)日：2012-09-11
申请号：US12507835
申请日：2009-07-23
申请人： Li Fung Chang , Yongqian Wang
发明人： Li Fung Chang , Yongqian Wang
IPC分类号： H03M13/03
CPC分类号： H04L1/0059 , H04L1/0003 , H04L1/0009 , H04L1/0026 , H04L1/0065 , H04L1/0068 , H04L1/0069 , H04L1/0071 , H04L1/1816 , H04L1/1819 , H04L1/1829 , H04L1/1835 , H04L1/1845 , H04L1/203 , H04L1/208 , H04L25/03006 , H04L25/03318 , H04L25/067 , H04L27/0008 , H04L2025/03401 , H04L2025/03407 , H04L2025/03726 , H04L2027/0038
摘要： A wireless device for implementing Incremental Redundancy (IR) operations includes an IR memory dedicated to storing data related to the IR operations. The IR memory includes a Type I IR memory adapted to store IR status information of a Radio Link Control (RLC) data block and a Type II IR memory adapted to store the RLC data block.
摘要翻译：用于实现增量冗余（IR）操作的无线设备包括专用于存储与IR操作有关的数据的IR存储器。 IR存储器包括适于存储无线电链路控制（RLC）数据块的IR状态信息的I型IR存储器和适于存储RLC数据块的II型IR存储器。

3. 发明授权

US08103022B2 Method and system for detecting, and controlling power for, an auxiliary microphone 有权
标题翻译：用于检测和控制辅助麦克风的电源的方法和系统
公开(公告)号：US08103022B2
公开(公告)日：2012-01-24
申请号：US11565576
申请日：2006-11-30
申请人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang , Andy Tong , Todd L. Brooks , Claude Hayek
发明人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang , Andy Tong , Todd L. Brooks , Claude Hayek
IPC分类号： H04R3/00 , H04B1/38
CPC分类号： H04R5/04 , H04R2420/01 , H04R2420/07 , H04R2499/11
摘要： Methods and systems for detecting, and controlling power for, an auxiliary microphone are disclosed. Aspects of one method may include a detection block intermittently enabling a bias circuit block to provide a bias signal to determine if an auxiliary microphone may be communicatively coupled to a mobile device. The detection block may process 1-bit digital samples received from the bias circuit bock to determine whether the auxiliary microphone may be communicatively coupled. The detection block may also process the 1-bit digital samples to determine if a button associated with the auxiliary microphone may have been pushed or activated.
摘要翻译：公开了用于检测和控制辅助麦克风的功率的方法和系统。一种方法的方面可以包括间歇地使得偏置电路块提供偏置信号以确定辅助麦克风是否可通信地耦合到移动设备的检测块。检测块可以处理从偏置电路块接收的1位数字样本，以确定辅助麦克风是否可以通信耦合。检测块还可以处理1位数字样本，以确定与辅助麦克风相关联的按钮是否可能被推动或激活。

4. 发明授权

US08068681B2 Method and system for pipelined processing in an integrated embedded image and video accelerator 有权
标题翻译：集成嵌入式图像和视频加速器中流水线处理的方法和系统
公开(公告)号：US08068681B2
公开(公告)日：2011-11-29
申请号：US12839591
申请日：2010-07-20
申请人： Taiyi Cheng , Mark Hahm , Li Fung Chang
发明人： Taiyi Cheng , Mark Hahm , Li Fung Chang
IPC分类号： G06K9/36
CPC分类号： H04N19/42
摘要： A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.
摘要翻译：描述了集成嵌入式图像和视频加速器中流水线处理的方法和系统。在集成嵌入式图像和视频加速器中用于流水线处理的系统的方面可以包括能够对单个芯片内的视频数据进行流水线处理的电路，其中流水线处理还可以包括对视频数据块进行解码，同时对先前解码的视频数据块。系统的方面还可以包括能够在单个芯片内转换所述视频数据的块的电路，同时在所述单个芯片内同时编码先前转换的视频数据块。

5. 发明申请

US20110222711A1 CONTROLLING GAIN DURING MULTIPATH MULTI-RATE AUDIO PROCESSING 有权
标题翻译：在多路径多音频处理中控制增益
公开(公告)号：US20110222711A1
公开(公告)日：2011-09-15
申请号：US13111660
申请日：2011-05-19
申请人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang
发明人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang
IPC分类号： H03G3/00
CPC分类号： H03G3/3026 , H03G3/3089
摘要： Methods and systems for processing audio signals are disclosed herein. Aspects of the method may comprise controlling gain during multipath, multi-rate audio processing by generating a digital signal that is a product of an input digital signal and a gain coefficient derived from a lookup table, and coarse tuning the gain by bit-shifting the digital signal to generate a digital output signal. The gain may be fine-tuned utilizing a variable step size determined by interpolation. The gain coefficient may be partitioned into gain blocks, which may be twice a corresponding value in preceding gain blocks. The gain blocks may be partitioned into steps that represent particular gain values within a range associated with the gain block. The digital output signal may be ramped utilizing a linear interpolation of the gain coefficients over a number of samples of the input signal, where the number of samples is given as a power of two.
摘要翻译：本文公开了用于处理音频信号的方法和系统。该方法的方面可以包括通过产生作为输入数字信号和从查找表导出的增益系数的乘积的数字信号来控制多路径，多速率音频处理中的增益，以及通过位移数字信号产生数字输出信号。可以利用通过插值确定的可变步长来微调增益。增益系数可以被划分为增益块，其可以是先前增益块中相应值的两倍。增益块可以被划分为在与增益块相关联的范围内表示特定增益值的步骤。数字输出信号可以通过对输入信号的多个样本的增益系数的线性内插来斜坡，其中样本数量被给予为2的幂。

6. 发明授权

US07949419B2 Method and system for controlling gain during multipath multi-rate audio processing 有权
标题翻译：多径多速率音频处理中控制增益的方法和系统
公开(公告)号：US07949419B2
公开(公告)日：2011-05-24
申请号：US11565358
申请日：2006-11-30
申请人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang
发明人： Hongwei Kong , Nelson Sollenberger , Li Fung Chang
IPC分类号： G06F17/00 , H03G3/00 , H04B1/06 , H04B7/00
CPC分类号： H03G3/3026 , H03G3/3089
摘要： Methods and systems for processing audio signals are disclosed herein. Aspects of the method may comprise controlling gain during multipath, multi-rate audio processing by generating via a digital gain circuit, a digital signal that is a product of an input digital signal and a gain coefficient derived from a lookup table, and bit-shifted to generate a digital output signal. The gain coefficient may be partitioned into a number of gain blocks. The gain values in each of the gain blocks may be twice a corresponding value in each preceding gain block. The gain blocks may be partitioned into steps that represent particular gain values within a range associated with the gain block. The digital output signal may be ramped utilizing a linear interpolation of the gain coefficients one step apart over a number of samples of the digital input signal, where the number of samples is given as a power of two.
摘要翻译：本文公开了用于处理音频信号的方法和系统。该方法的方面可以包括通过经由数字增益电路产生多径，多速率音频处理中的增益，作为输入数字信号的乘积的数字信号和从查找表导出的增益系数，以及位移以产生数字输出信号。增益系数可以被划分成多个增益块。每个增益块中的增益值可以是每个先前增益块中相应值的两倍。增益块可以被划分为在与增益块相关联的范围内表示特定增益值的步骤。数字输出信号可以通过对数字输入信号的数量样本间隔一步的增益系数的线性内插来斜坡，其中样本数量被给予为2的幂。

7. 发明授权

US07885319B2 Multiple branch PSYNC detection module 失效
标题翻译：多分支PSYNC检测模块
公开(公告)号：US07885319B2
公开(公告)日：2011-02-08
申请号：US11852828
申请日：2007-09-10
申请人： Mark David Hahm , Wei Luo , Li Fung Chang , Nelson R. Sollenberger , Hendrik Johannes Conroy
发明人： Mark David Hahm , Wei Luo , Li Fung Chang , Nelson R. Sollenberger , Hendrik Johannes Conroy
IPC分类号： H04B1/00
CPC分类号： H04B1/7075 , H04B2201/70722 , H04B2201/70728
摘要： A wireless terminal is operable to receive a Wideband Code Division Multiple Access (WCDMA) signal from a base station and includes clock circuitry, a wireless interface, and a Primary Synchronization (PSYNC) module. The clock circuitry generates a wireless terminal clock using a wireless terminal oscillator. The wireless interface receives the WCDMA signal, which is produced by the base station using a base station clock that is produced using a base station oscillator that is more accurate than the wireless terminal oscillator. The PSYNC module includes a plurality of PSYNC correlation branches. Each PSYNC correlation branch phase rotates the WCDMA signal based upon a respective frequency offset, correlates the phase rotated WCDMA signal with a Primary Synchronization Channel (PSCH) code over a plurality of sampling positions, and produces PSYNC correlation energies based upon the correlations for each of the plurality of sampling positions.
摘要翻译：无线终端可操作以从基站接收宽带码分多址（WCDMA）信号，并包括时钟电路，无线接口和主同步（PSYNC）模块。时钟电路使用无线终端振荡器产生无线终端时钟。无线接口接收由基站使用基站振荡器产生的WCDMA信号，该基站时钟是使用比无线终端振荡器更准确的基站振荡器产生的。 PSYNC模块包括多个PSYNC相关分支。每个PSYNC相关分支相位基于相应的频率偏移旋转WCDMA信号，将相位旋转的WCDMA信号与多个采样位置上的主同步信道（PSCH）码相关联，并且基于每个的相关性产生PSYNC相关能量多个采样位置。

8. 发明授权

US07760951B2 Method and system for pipelined processing in an integrated embedded image and video accelerator 有权
标题翻译：集成嵌入式图像和视频加速器中流水线处理的方法和系统
公开(公告)号：US07760951B2
公开(公告)日：2010-07-20
申请号：US11353528
申请日：2006-02-14
申请人： Taiyi Cheng , Mark Hahm , Li Fung Chang
发明人： Taiyi Cheng , Mark Hahm , Li Fung Chang
IPC分类号： G06K9/36
CPC分类号： H04N19/42
摘要： A method and system for pipelined processing in an integrated embedded image and video accelerator is described. Aspects of a system for pipelined processing in an integrated embedded image and video accelerator may include circuitry that enables pipeline processing of video data within a single chip, wherein the pipeline processing may further include decoding of a block of video data while simultaneously inverse transforming a previously decoded block of video data. Aspects of the system may also include circuitry that enables transformation, within the single chip, of a block of said video data while simultaneously encoding, within said single chip, a previously transformed block of video data.
摘要翻译：描述了集成嵌入式图像和视频加速器中流水线处理的方法和系统。在集成嵌入式图像和视频加速器中用于流水线处理的系统的方面可以包括能够对单个芯片内的视频数据进行流水线处理的电路，其中流水线处理还可以包括对视频数据块进行解码，同时对先前解码的视频数据块。系统的方面还可以包括能够在单个芯片内转换所述视频数据的块的电路，同时在所述单个芯片内同时编码先前转换的视频数据块。

9. 发明申请

US20100135377A1 FREQUENCY DOMAIN EQUALIZER FOR DUAL ANTENNA RADIO 有权
标题翻译：用于双天线无线电的频域均衡器
公开(公告)号：US20100135377A1
公开(公告)日：2010-06-03
申请号：US12703311
申请日：2010-02-10
申请人： Junqiang Li , Mark David Hahm , Nelson R. Sollenberger , Li Fung Chang
发明人： Junqiang Li , Mark David Hahm , Nelson R. Sollenberger , Li Fung Chang
IPC分类号： H04B1/10 , H03K5/159
CPC分类号： H04L25/03038 , H04L25/0204 , H04L25/0212 , H04L25/022 , H04L2025/03426 , H04L2025/03605
摘要： A Radio Frequency (RF) receiver includes a RF front end and a baseband processing module coupled to the RF front end that is operable to receive a time domain signal that includes time domain training symbols and time domain data symbols. The baseband processing module includes a channel estimator operable to process the time domain training symbols to produce a time domain channel estimate, a Fast Fourier Transformer operable to convert the time domain channel estimate to the frequency domain to produce a frequency domain channel estimate, a weight calculator operable to produce frequency domain equalizer coefficients based upon the frequency domain channel estimate, an Inverse Fast Fourier Transformer operable to converting the frequency domain equalizer coefficients to the time domain to produce time domain equalizer coefficients, and an equalizer operable to equalize the time domain data symbols using the time domain equalizer coefficients.
摘要翻译：射频（RF）接收机包括RF前端和耦合到RF前端的基带处理模块，其可操作以接收包括时域训练符号和时域数据符号的时域信号。基带处理模块包括信道估计器，其可操作以处理时域训练符号以产生时域信道估计;快速傅立叶变换器，其可操作以将时域信道估计转换为频域以产生频域信道估计，权重计算器，其可操作以基于频域信道估计产生频域均衡器系数;反傅里叶变换器，其可操作以将频域均衡器系数转换到时域以产生时域均衡器系数;以及均衡器，其可操作以均衡时域数据符号使用时域均衡器系数。

10. 发明授权

US07729454B2 Method and system for signal phase variation detection in communication systems 有权
标题翻译：通信系统信号相位变化检测方法与系统
公开(公告)号：US07729454B2
公开(公告)日：2010-06-01
申请号：US11565082
申请日：2006-11-30
申请人： Li Fung Chang , Hongwei Kong , Nelson Sollenberger
发明人： Li Fung Chang , Hongwei Kong , Nelson Sollenberger
IPC分类号： H04L27/00
CPC分类号： H04L25/0228 , H04L2027/0067
摘要： Aspects of a method and system for signal phase variation detection in communication systems are presented. Aspects of the system may enable detection of phase change between a current received symbol, and one or more previous received symbols. Based on the phase change a channel estimation filter bandwidth may be selected for despreading and/or descrambling one or more subsequent received symbols. In addition, a decision may be made as to whether the subsequent received symbols are to be received based on a closed loop system, or based on an open loop system.
摘要翻译：介绍了通信系统信号相位变化检测方法和系统的方面。系统的方面可以使得能够检测当前接收符号与一个或多个先前接收的符号之间的相位变化。基于相位改变，可以选择信道估计滤波器带宽用于解扩和/或解扰一个或多个后续接收符号。此外，可以基于闭环系统或基于开环系统来确定是否要接收后续接收到的符号。

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